soc: add realtek amebadplus SOC integration

Add initial version of Amebadplus Soc integration

Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>

Author: zjian-zhang

soc/realtek/ameba/CMakeLists.txt

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(common)
+
+add_subdirectory(common)
+add_subdirectory(${CONFIG_SOC})

soc/realtek/ameba/Kconfig

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+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_REALTEK_AMEBA
+	select BUILD_OUTPUT_HEX
+	select SOC_EARLY_INIT_HOOK
+
+if SOC_FAMILY_REALTEK_AMEBA
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_REALTEK_AMEBA

soc/realtek/ameba/Kconfig.defconfig

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+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_REALTEK_AMEBA
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_REALTEK_AMEBA

soc/realtek/ameba/Kconfig.soc

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+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_REALTEK_AMEBA
+	bool
+
+config SOC_FAMILY
+	default "realtek_ameba" if SOC_FAMILY_REALTEK_AMEBA
+
+rsource "*/Kconfig.soc"

soc/realtek/ameba/amebadplus/CMakeLists.txt

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_include_directories(.)
+
+zephyr_sources(soc.c)
+
+zephyr_linker_sources(SECTIONS boot_section.ld)
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/realtek/ameba/amebadplus/Kconfig

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+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_AMEBADPLUS
+	select ARM
+	select CPU_CORTEX_M55
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_FPU
+	select CPU_HAS_VFP
+	select ARMV8_M_DSP
+	select CPU_HAS_ARM_MPU
+	select ARM_MPU
+	select ARM_TRUSTZONE_M

soc/realtek/ameba/amebadplus/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_AMEBADPLUS
+
+config NUM_IRQS
+	default 96
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_sys,clock-frequency)
+
+config CACHE_MANAGEMENT
+	default y
+
+endif #SOC_AMEBADPLUS

soc/realtek/ameba/amebadplus/Kconfig.soc

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+# Copyright (c) 2024 Realtek Semiconductor Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_AMEBADPLUS
+	bool
+	select SOC_FAMILY_REALTEK_AMEBA
+
+config SOC
+	default "amebadplus" if SOC_AMEBADPLUS
+
+config ARM_CORE_CM4
+	bool
+	default y if SOC_AMEBADPLUS

soc/realtek/ameba/amebadplus/boot_section.ld

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+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.ram_image2.entry,,SUBALIGN(32))
+{
+	__image2_entry_func__ = .;
+	KEEP(*(SORT(.image2.entry.data*)))
+	. = ALIGN(32);
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+SECTION_PROLOGUE(.psram_image2.text.data,,SUBALIGN(32))
+{
+	. = ALIGN (32);
+	__ipc_table_start__ = .;
+	KEEP(*(*.ipc.table.data*))
+	__ipc_table_end__ = .;
+} GROUP_LINK_IN(ROMABLE_REGION)

soc/realtek/ameba/amebadplus/soc.c

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+/*
+ * Copyright (c) 2024 Realtek Semiconductor Corp.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <soc.h>
+#include <ameba_soc.h>
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/cache.h>
+
+void z_arm_reset(void);
+
+IMAGE2_ENTRY_SECTION
+RAM_START_FUNCTION Img2EntryFun0 = {z_arm_reset, NULL, /* BOOT_RAM_WakeFromPG, */
+				    (uint32_t)NewVectorTable};
+
+void soc_early_init_hook(void)
+{
+	/*
+	 * Cache is enabled by default at reset, disable it before
+	 * sys_cache*-functions can enable them.
+	 */
+	Cache_Enable(DISABLE);
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+
+	XTAL_INIT();
+
+	if (SYSCFG_CHIPType_Get() == CHIP_TYPE_ASIC_POSTSIM) { /* Only Asic need OSC Calibration */
+		OSC4M_Init();
+		OSC4M_Calibration(30000);
+		if ((((BOOT_Reason()) & AON_BIT_RSTF_DSLP) == FALSE)) {
+			OSC131K_Calibration(30000); /* PPM=30000=3% */ /* 7.5ms */
+		}
+	}
+}