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arch: microblaze: Support files (Minimal Board Support Package)
Internal references: FWRIVERHD-4980,FWRIVERHD-4990 Signed-off-by: Alp Sayin <alpsayin@gmail.com>
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‎arch/microblaze/core/microblaze_disable_dcache.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_disable_dcache
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.ent microblaze_disable_dcache
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.balign 4
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microblaze_disable_dcache:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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#if CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
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addik r1, r1, -8
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swi r15, r1, 0
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/* microblaze_flush_dcache does not use r1*/
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brlid r15, microblaze_flush_dcache
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nop
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lwi r15, r1, 0
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addik r1, r1, 8
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#endif /* CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
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rtsd r15, 8
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msrclr r0, 0x80
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#else /* CONFIG_MICROBLAZE_USE_MSR_INSTR == 1 */
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addik r1, r1, -8
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#if CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
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swi r15, r1, 0
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brlid r15, microblaze_flush_dcache
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nop
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#endif /* CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
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mfs r11, rmsr
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andi r11, r11, ~(0x80)
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mts rmsr, r11
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#if CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0
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lwi r15, r1, 0
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#endif /* CONFIG_MICROBLAZE_DCACHE_USE_WRITEBACK != 0 */
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addik r1, r1, 8
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rtsd r15, 8
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nop
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_disable_dcache

‎arch/microblaze/core/microblaze_disable_exceptions.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_disable_exceptions
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.ent microblaze_disable_exceptions
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.balign 4
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microblaze_disable_exceptions:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrclr r0, 0x100
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#else
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mfs r4, rmsr;
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/* Turn OFF the EE bit */
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andi r4, r4, ~(0x100);
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mts rmsr, r4;
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rtsd r15, 8;
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nop;
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#endif
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.end microblaze_disable_exceptions

‎arch/microblaze/core/microblaze_disable_icache.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_disable_icache
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.ent microblaze_disable_icache
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.balign 4
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microblaze_disable_icache:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrclr r0, 0x20
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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#Read the MSR register
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mfs r8, rmsr
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#Clear the icache enable bit
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andi r8, r8, ~(0x20)
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#Save the MSR register
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mts rmsr, r8
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#Return
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rtsd r15, 8
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nop
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#endif
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.end microblaze_disable_icache

‎arch/microblaze/core/microblaze_disable_interrupts.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_disable_interrupts
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.ent microblaze_disable_interrupts
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.balign 4
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microblaze_disable_interrupts:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrclr r0, 0x2
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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#Read the MSR register
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mfs r12, rmsr
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#Clear the interrupt enable bit
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andi r12, r12, ~(0x2)
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#Save the MSR register
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mts rmsr, r12
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#Return
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rtsd r15, 8
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nop
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_disable_interrupts

‎arch/microblaze/core/microblaze_enable_dcache.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_enable_dcache
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.ent microblaze_enable_dcache
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.balign 4
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microblaze_enable_dcache:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrset r0, 0x80
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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#Read the MSR register
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mfs r8, rmsr
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#Set the interrupt enable bit
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ori r8, r8, 0x80
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#Save the MSR register
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mts rmsr, r8
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#Return
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rtsd r15, 8
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nop
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_enable_dcache

‎arch/microblaze/core/microblaze_enable_exceptions.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_enable_exceptions
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.ent microblaze_enable_exceptions
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.balign 4
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microblaze_enable_exceptions:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8;
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msrset r0, 0x100
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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mfs r4, rmsr;
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/* Turn ON the EE bit */
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ori r4, r4, 0x100;
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mts rmsr, r4;
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rtsd r15, 8;
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nop;
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_enable_exceptions

‎arch/microblaze/core/microblaze_enable_icache.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_enable_icache
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.ent microblaze_enable_icache
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.balign 4
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microblaze_enable_icache:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrset r0, 0x20
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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#Read the MSR register
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mfs r8, rmsr
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#Set the interrupt enable bit
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ori r8, r8, 0x20
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#Save the MSR register
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mts rmsr, r8
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#Return
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rtsd r15, 8
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nop
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_enable_icache

‎arch/microblaze/core/microblaze_enable_interrupts.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.text
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.globl microblaze_enable_interrupts
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.ent microblaze_enable_interrupts
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.balign 4
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microblaze_enable_interrupts:
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#if CONFIG_MICROBLAZE_USE_MSR_INSTR == 1
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rtsd r15, 8
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msrset r0, 0x2
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nop
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#else /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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#Read the MSR register
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mfs r12, rmsr
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#Set the interrupt enable bit
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ori r12, r12, 0x2
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#Save the MSR register
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mts rmsr, r12
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#Return
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rtsd r15, 8
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nop
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#endif /*CONFIG_MICROBLAZE_USE_MSR_INSTR == 1*/
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.end microblaze_enable_interrupts

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