include: binding defines division factor for stm32 MCO prescaler

Depending on the stm32 serie the MCO1/2 prescaler is a value
set in the CFGR register to divide the MCO output clock.
Use the same model based on the RefMan for other stm32 series
than stm32C0/F4/F7/H5/H7, once the MCO is in the DTS.

Signed-off-by: Francois Ramu <francois.ramu@st.com>

Author: FRASTM

dts/bindings/clock/st,stm32-clock-mco.yaml

@@ -15,7 +15,7 @@ description: |
         Example:
                 &mco1 {
                         clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>;
-                        prescaler = <MCO1_PRE(1)>;
+                        prescaler = <MCO1_PRE(MCO_PRE_DIV_5)>;
                         pinctrl-0 = <&rcc_mco_pa8>;
                         pinctrl-names = "default";
                         status = "okay";

include/zephyr/dt-bindings/clock/stm32c0_clock.h

@@ -81,4 +81,14 @@
 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
 
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1   0
+#define MCO_PRE_DIV_2   1
+#define MCO_PRE_DIV_4   2
+#define MCO_PRE_DIV_8   3
+#define MCO_PRE_DIV_16  4
+#define MCO_PRE_DIV_32  5
+#define MCO_PRE_DIV_64  6
+#define MCO_PRE_DIV_128 7
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f4_clock.h

@@ -82,4 +82,11 @@
 /** BDCR devices */
 #define RTC_SEL(val)  STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
 
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 0
+#define MCO_PRE_DIV_2 4
+#define MCO_PRE_DIV_3 5
+#define MCO_PRE_DIV_4 6
+#define MCO_PRE_DIV_5 7
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32f7_clock.h

@@ -82,6 +82,14 @@
 #define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
+
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 0
+#define MCO_PRE_DIV_2 4
+#define MCO_PRE_DIV_3 5
+#define MCO_PRE_DIV_4 6
+#define MCO_PRE_DIV_5 7
+
 /** BDCR devices */
 #define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
 

include/zephyr/dt-bindings/clock/stm32h5_clock.h

@@ -156,4 +156,21 @@
 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG)
 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0xF, 29, CFGR1_REG)
 
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 1
+#define MCO_PRE_DIV_2 2
+#define MCO_PRE_DIV_3 3
+#define MCO_PRE_DIV_4 4
+#define MCO_PRE_DIV_5 5
+#define MCO_PRE_DIV_6 6
+#define MCO_PRE_DIV_7 7
+#define MCO_PRE_DIV_8 8
+#define MCO_PRE_DIV_9 9
+#define MCO_PRE_DIV_10 10
+#define MCO_PRE_DIV_11 11
+#define MCO_PRE_DIV_12 12
+#define MCO_PRE_DIV_13 13
+#define MCO_PRE_DIV_14 14
+#define MCO_PRE_DIV_15 15
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32h7_clock.h

@@ -141,4 +141,21 @@
 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)
 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)
 
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 1
+#define MCO_PRE_DIV_2 2
+#define MCO_PRE_DIV_3 3
+#define MCO_PRE_DIV_4 4
+#define MCO_PRE_DIV_5 5
+#define MCO_PRE_DIV_6 6
+#define MCO_PRE_DIV_7 7
+#define MCO_PRE_DIV_8 8
+#define MCO_PRE_DIV_9 9
+#define MCO_PRE_DIV_10 10
+#define MCO_PRE_DIV_11 11
+#define MCO_PRE_DIV_12 12
+#define MCO_PRE_DIV_13 13
+#define MCO_PRE_DIV_14 14
+#define MCO_PRE_DIV_15 15
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */

include/zephyr/dt-bindings/clock/stm32h7rs_clock.h

@@ -137,4 +137,21 @@
 #define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG)
 #define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG)
 
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 1
+#define MCO_PRE_DIV_2 2
+#define MCO_PRE_DIV_3 3
+#define MCO_PRE_DIV_4 4
+#define MCO_PRE_DIV_5 5
+#define MCO_PRE_DIV_6 6
+#define MCO_PRE_DIV_7 7
+#define MCO_PRE_DIV_8 8
+#define MCO_PRE_DIV_9 9
+#define MCO_PRE_DIV_10 10
+#define MCO_PRE_DIV_11 11
+#define MCO_PRE_DIV_12 12
+#define MCO_PRE_DIV_13 13
+#define MCO_PRE_DIV_14 14
+#define MCO_PRE_DIV_15 15
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */