tests: interrupt_util: Update RX irq trigger method

The QEMU RX doesn't allow to write value to IR flag,
There is also mentioned in RX HWM that the IR should
not be write 1 to. So we change the method to trigger
interrupt here is to call directly to SW irq table

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>

Author: duynguyenxa

subsys/testsuite/include/zephyr/interrupt_util.h

@@ -58,9 +58,9 @@ static inline uint32_t get_available_nvic_line(uint32_t initial_offset)
 static inline void trigger_irq(int irq)
 {
 	printk("Triggering irq : %d\n", irq);
-#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) \
-	|| defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M1)\
-	|| defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) || defined(CONFIG_CPU_CORTEX_M0) ||                       \
+	defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M1) ||                      \
+	defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 	/* QEMU does not simulate the STIR register: this is a workaround */
 	NVIC_SetPendingIRQ(irq);
 #else
@@ -84,8 +84,7 @@ static inline void trigger_irq(int irq)
 	 * requesting CPU.
 	 */
 #if CONFIG_GIC_VER <= 2
-	sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
-		    GICD_SGIR);
+	sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq), GICD_SGIR);
 #else
 	uint64_t mpidr = GET_MPIDR();
 	uint8_t aff0 = MPIDR_AFFLVL(mpidr, 0);
@@ -108,7 +107,7 @@ static inline void trigger_irq(int irq)
 #define VECTOR_MASK 0xFF
 #else
 #include <zephyr/arch/arch_interface.h>
-#define LOAPIC_ICR_IPI_TEST  0x00004000U
+#define LOAPIC_ICR_IPI_TEST 0x00004000U
 #endif
 
 /*
@@ -175,9 +174,7 @@ static inline void trigger_irq(int irq)
 {
 	uint32_t mip;
 
-	__asm__ volatile ("csrrs %0, mip, %1\n"
-			  : "=r" (mip)
-			  : "r" (1 << irq));
+	__asm__ volatile("csrrs %0, mip, %1\n" : "=r"(mip) : "r"(1 << irq));
 }
 #endif
 #elif defined(CONFIG_XTENSA)
@@ -218,7 +215,8 @@ static inline void trigger_irq(int irq)
 	__ASSERT(irq < CONFIG_NUM_IRQS, "attempting to trigger invalid IRQ (%u)", irq);
 	__ASSERT(irq >= CONFIG_GEN_IRQ_START_VECTOR, "attempting to trigger reserved IRQ (%u)",
 		 irq);
-	WRITE_BIT(REG(IR_BASE_ADDRESS + irq), 0, true);
+	_sw_isr_table[irq - CONFIG_GEN_IRQ_START_VECTOR].isr(
+		_sw_isr_table[irq - CONFIG_GEN_IRQ_START_VECTOR].arg);
 }
 
 #else