drivers: sdhc: Add support for Apollo510 SDIO host

This commit adds support for ambiq SDIO host driver

Signed-off-by: Fan Wang <fan.wang@ambiq.com>

Author: fanwang-ambiq

boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi

@@ -380,4 +380,78 @@
 			drive-strength = "0.5";
 		};
 	};
+
+	sdio0_default: sdio0_default {
+		group0 {
+			pinmux = <SDIF0_DAT1_P85>,
+				 <SDIF0_DAT3_P87>,
+				 <SDIF0_DAT4_P156>,
+				 <SDIF0_DAT5_P157>,
+				 <SDIF0_DAT6_P158>,
+				 <SDIF0_DAT7_P159>;
+				 drive-strength = "1.0";
+		};
+		group1 {
+			pinmux = <SDIF0_DAT0_P84>,
+				 <SDIF0_DAT2_P86>,
+				 <SDIF0_CMD_P160>,
+				 <SDIF0_CLKOUT_P88>;
+				 drive-strength = "1.0";
+				 bias-pull-up;
+				 ambiq,pull-up-ohms = <12000>;
+		};
+		group2 {
+			pinmux = <GPIO_P161>;
+				 ambiq,sdif-cdwp = <1>;
+		};
+		group3 {
+			pinmux = <GPIO_P175>;
+				 ambiq,sdif-cdwp = <2>;
+		};
+		group4 {
+			pinmux = <GPIO_P161>;
+				 ambiq,sdif-cdwp = <3>;
+		};
+		group5 {
+			pinmux = <GPIO_P175>;
+				 ambiq,sdif-cdwp = <4>;
+		};
+	};
+
+	sdio1_default: sdio1_default {
+		group0 {
+			pinmux = <SDIF1_DAT1_P126>,
+				 <SDIF1_DAT3_P128>,
+				 <SDIF1_DAT4_P130>,
+				 <SDIF1_DAT5_P131>,
+				 <SDIF1_DAT6_P132>,
+				 <SDIF1_DAT7_P133>;
+				 drive-strength = "1.0";
+		};
+		group1 {
+			pinmux = <SDIF1_DAT0_P125>,
+				 <SDIF1_DAT2_P127>,
+				 <SDIF1_CMD_P134>,
+				 <SDIF1_CLKOUT_P129>;
+				 drive-strength = "1.0";
+				 bias-pull-up;
+				 ambiq,pull-up-ohms = <12000>;
+		};
+		group2 {
+			pinmux = <GPIO_P161>;
+				 ambiq,sdif-cdwp = <1>;
+		};
+		group3 {
+			pinmux = <GPIO_P175>;
+				 ambiq,sdif-cdwp = <2>;
+		};
+		group4 {
+			pinmux = <GPIO_P161>;
+				 ambiq,sdif-cdwp = <3>;
+		};
+		group5 {
+			pinmux = <GPIO_P175>;
+				 ambiq,sdif-cdwp = <4>;
+		};
+	};
 };

boards/ambiq/apollo510_evb/apollo510_evb.dts

@@ -199,6 +199,19 @@
 	};
 };
 
+&sdio0 {
+	pinctrl-0 = <&sdio0_default>;
+	pinctrl-names = "default";
+	txdelay = <0>;
+	rxdelay = <0>;
+	status = "disabled";
+	mmc {
+		compatible = "zephyr,mmc-disk";
+		disk-name = "SD2";
+		status = "disabled";
+	};
+};
+
 zephyr_udc0: &usb {
 	vddusb33-gpios = <&gpio64_95 27 (GPIO_PULL_UP)>;
 	vddusb0p9-gpios = <&gpio64_95 26 (GPIO_PULL_UP)>;

boards/ambiq/apollo510_evb/apollo510_evb.yaml

@@ -20,6 +20,7 @@ supported:
   - clock_control
   - usbd
   - mspi
+  - sdio
 testing:
   ignore_tags:
     - net

dts/arm/ambiq/ambiq_apollo510.dtsi

@@ -559,6 +559,22 @@
 			#io-channel-cells = <1>;
 		};
 
+		sdio0: sdio@SDIO0_BASE_NAME {
+			compatible = "ambiq,sdio";
+			reg = <SDIO0_REG_BASE SDIO0_REG_SIZE>;
+			interrupts = <26 0>;
+			status = "disabled";
+			zephyr,pm-device-runtime-auto;
+		};
+
+		sdio1: sdio@SDIO1_BASE_NAME {
+			compatible = "ambiq,sdio";
+			reg = <SDIO1_REG_BASE SDIO1_REG_SIZE>;
+			interrupts = <84 0>;
+			status = "disabled";
+			zephyr,pm-device-runtime-auto;
+		};
+
 		pinctrl: pin-controller@GPIO_BASE_NAME {
 			compatible = "ambiq,apollo5-pinctrl";
 			reg = <GPIO_REG_BASE GPIO_REG_SIZE>;

samples/subsys/fs/fs_sample/boards/apollo510_evb.conf

@@ -0,0 +1,16 @@
+CONFIG_DISK_DRIVER_MMC=y
+CONFIG_MMC_STACK=y
+CONFIG_SDHC=y
+CONFIG_MMC_SUBSYS=y
+
+CONFIG_MAIN_STACK_SIZE=8192
+CONFIG_IDLE_STACK_SIZE=4096
+CONFIG_AMBIQ_SDIO_ASYNC=y
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_RUNTIME=y
+CONFIG_MMC_DDR50=y
+CONFIG_MMC_CARD_8BIT_WIDTH=y
+
+CONFIG_ICACHE=y
+CONFIG_DCACHE=n

samples/subsys/fs/fs_sample/boards/apollo510_evb.overlay

@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2025 Ambiq Micro Inc. <www.ambiq.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		sdhc0 = &sdio0;
+	};
+};
+
+&sdio0 {
+	status = "okay";
+	mmc {
+		status = "okay";
+	};
+};

samples/subsys/fs/fs_sample/sample.yaml

@@ -82,3 +82,8 @@ tests:
   sample.filesystem.fat_fs.stm32h747i_disco_m7_sdmmc:
     build_only: true
     platform_allow: stm32h747i_disco/stm32h747xx/m7
+  sample.filesystem.fat_fs.apollo510_evb_sdmmc:
+    build_only: true
+    platform_allow: apollo510_evb
+    extra_args:
+      - OVERLAY_CONFIG=boards/apollo510_evb.conf

subsys/sd/Kconfig

@@ -28,6 +28,36 @@ config SD_STACK
 	help
 	  Enable SD card support.
 
+if SDIO_STACK
+config SDIO_CARD_1BIT_WIDTH
+	bool "SDIO CARD 1 bit width support"
+	default n
+	help
+	  Enable SDIO card 1 bit width mode.
+endif # SDIO_STACK
+
+if MMC_STACK
+
+config MMC_DDR50
+	bool "MMC DDR50 mode support"
+	default n
+	help
+	  Enable MMC DDR50 mode.
+
+config MMC_CARD_4BIT_WIDTH
+	bool "MMC CARD 4 bit width support"
+	default n
+	help
+	  Enable MMC card 4 bit width mode.
+
+config MMC_CARD_8BIT_WIDTH
+	bool "MMC CARD 8 bit width support"
+	default n
+	help
+	  Enable MMC card 8 bit width mode.
+
+endif # MMC_STACK
+
 if SD_STACK
 
 module = SD

subsys/sd/mmc.c

@@ -29,6 +29,9 @@
 #define MMC_SWITCH_8_BIT_BUS_ARG                                                                   \
 	(0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) +    \
 		(0x0000FF00 & (2U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
+#define MMC_SWITCH_4_BIT_DDR_BUS_ARG                                                               \
+	(0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) +    \
+		(0x0000FF00 & (5U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
 #define MMC_SWITCH_4_BIT_BUS_ARG                                                                   \
 	(0xFC000000 & (0U << 26)) + (0x03000000 & (0b11 << 24)) + (0x00FF0000 & (183U << 16)) +    \
 		(0x0000FF00 & (1U << 8)) + (0x000000F7 & (0U << 3)) + (0x00000000 & (3U << 0))
@@ -89,8 +92,25 @@ static inline int mmc_set_max_freq(struct sd_card *card, struct sd_csd *card_csd
 /* Sends CMD6 to switch bus width*/
 static int mmc_set_bus_width(struct sd_card *card);
 
+#ifdef CONFIG_MMC_DDR50
+/* Sets card to DDR50 mode (using CMD6) */
+static int mmc_set_ddr50_timing(struct sd_card *card, struct mmc_ext_csd *card_ext_csd);
+#else
 /* Sets card to the fastest timing mode (using CMD6) and SDHC to max frequency */
 static int mmc_set_timing(struct sd_card *card, struct mmc_ext_csd *card_ext_csd);
+#endif /*CONFIG_MMC_DDR50*/
+
+/* Sets card timing mode (e.g., DDR50, HS) based on configuration */
+static int mmc_set_timing_mode(struct sd_card *card, struct mmc_ext_csd *card_ext_csd)
+{
+#ifdef CONFIG_MMC_DDR50
+	/* DDR50 mode logic */
+	return mmc_set_ddr50_timing(card, card_ext_csd);
+#else
+	/* Fastest timing mode logic */
+	return mmc_set_timing(card, card_ext_csd);
+#endif /* CONFIG_MMC_DDR50 */
+}
 
 /* Enable cache for emmc if applicable */
 static int mmc_set_cache(struct sd_card *card, struct mmc_ext_csd *card_ext_csd);
@@ -177,8 +197,8 @@ int mmc_card_init(struct sd_card *card)
 		return ret;
 	}
 
-	/* Set timing to fastest supported */
-	ret = mmc_set_timing(card, &card_ext_csd);
+	/* Sets card timing mode */
+	ret = mmc_set_timing_mode(card, &card_ext_csd);
 	if (ret) {
 		return ret;
 	}
@@ -372,6 +392,12 @@ static int mmc_set_bus_width(struct sd_card *card)
 	int ret;
 	struct sdhc_command cmd = {0};
 
+#if defined(CONFIG_MMC_CARD_8BIT_WIDTH)
+	card->bus_width = 8;
+#elif defined(CONFIG_MMC_CARD_4BIT_WIDTH)
+	card->bus_width = 4;
+#endif
+
 	if (card->host_props.host_caps.bus_8_bit_support && card->bus_width == 8) {
 		cmd.arg = MMC_SWITCH_8_BIT_BUS_ARG;
 		card->bus_io.bus_width = SDHC_BUS_WIDTH8BIT;
@@ -404,6 +430,57 @@ static int mmc_set_bus_width(struct sd_card *card)
 	return ret;
 }
 
+#ifdef CONFIG_MMC_DDR50
+static int mmc_set_ddr50_timing(struct sd_card *card, struct mmc_ext_csd *ext)
+{
+	int ret = 0;
+	struct sdhc_command cmd = {0};
+
+	if (ext->device_type.MMC_HS_DDR_1800MV && card->host_props.host_caps.ddr50_support &&
+	    (card->bus_io.bus_width >= SDHC_BUS_WIDTH4BIT)) {
+
+		cmd.arg = MMC_SWITCH_HS_TIMING_ARG;
+		cmd.opcode = SD_SWITCH;
+		cmd.response_type = SD_RSP_TYPE_R1b;
+		cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT;
+		ret = sdhc_request(card->sdhc, &cmd, NULL);
+		sdmmc_wait_ready(card);
+		if (ret) {
+			LOG_ERR("Setting HS Timing mode failed: %d", ret);
+			return ret;
+		}
+
+		if (card->bus_io.bus_width == SDHC_BUS_WIDTH4BIT) {
+			cmd.arg = MMC_SWITCH_4_BIT_DDR_BUS_ARG;
+		} else {
+			cmd.arg = MMC_SWITCH_8_BIT_DDR_BUS_ARG;
+		}
+		cmd.opcode = SD_SWITCH;
+		cmd.response_type = SD_RSP_TYPE_R1b;
+		cmd.timeout_ms = CONFIG_SD_CMD_TIMEOUT;
+		ret = sdhc_request(card->sdhc, &cmd, NULL);
+		sdmmc_wait_ready(card);
+		if (ret) {
+			LOG_ERR("Setting DDR data bus width failed: %d", ret);
+			return ret;
+		}
+
+		/* Max frequency in DDR50 mode is 52 MHz */
+		card->bus_io.clock = MMC_CLOCK_DDR52;
+		card->bus_io.timing = SDHC_TIMING_DDR52;
+		/* Change SDHC bus timing */
+		ret = sdhc_set_io(card->sdhc, &card->bus_io);
+		if (ret) {
+			return ret;
+		}
+		card->card_speed = MMC_HS_TIMING;
+	} else {
+		return -ENOTSUP;
+	}
+
+	return ret;
+}
+#else
 static int mmc_set_hs_timing(struct sd_card *card)
 {
 	int ret = 0;
@@ -557,6 +634,7 @@ static int mmc_set_timing(struct sd_card *card, struct mmc_ext_csd *ext)
 	}
 	return ret;
 }
+#endif /*CONFIG_MMC_DDR50*/
 
 static int mmc_read_ext_csd(struct sd_card *card, struct mmc_ext_csd *card_ext_csd)
 {

subsys/sd/sdio.c

@@ -58,6 +58,10 @@ static int sdio_send_ocr(struct sd_card *card, uint32_t ocr)
 				/* Card is not a supported SD device */
 				return -ENOTSUP;
 			}
+
+			/* Save OCR value from CMD5 response */
+			card->ocr = cmd.response[0];
+
 			/* Card has IO present, return zero to
 			 * indicate SDIO card
 			 */
@@ -567,6 +571,9 @@ int sdio_card_init(struct sd_card *card)
 		/* See if the card also supports 1.8V */
 		ocr_arg |= SD_OCR_SWITCH_18_REQ_FLAG;
 	}
+	/* Set OCR_ARG based on OCR value */
+	ocr_arg = card->ocr & 0x01FFFF00;
+
 	ret = sdio_send_ocr(card, ocr_arg);
 	if (ret) {
 		return ret;
@@ -646,7 +653,11 @@ int sdio_card_init(struct sd_card *card)
 		((card->cccr_flags & SDIO_SUPPORT_HS) ||
 		(card->cccr_flags & SDIO_SUPPORT_4BIT_LS_BUS))) {
 		/* Raise bus width to 4 bits */
+#ifdef CONFIG_SDIO_CARD_1BIT_WIDTH
+		ret = sdio_set_bus_width(card, SDHC_BUS_WIDTH1BIT);
+#else
 		ret = sdio_set_bus_width(card, SDHC_BUS_WIDTH4BIT);
+#endif
 		if (ret) {
 			return ret;
 		}