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soc: nxp: Add kw45 SoC support
kw45 SoC is similar to mcxw71 with minor differences in Radio Link Layer Interrupt and link layer configuration and status registers. Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
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‎soc/nxp/kinetis/kw45/CMakeLists.txt

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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(../../mcx/mcxw/soc.c ../../mcx/mcxw/mcxw71_platform_init.S)
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zephyr_include_directories(../../mcx/mcxw/)
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zephyr_sources_ifdef(CONFIG_NXP_NBU
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../../common/nxp_nbu.c
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)
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zephyr_include_directories(.)
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zephyr_sources_ifdef(
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CONFIG_PM
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power.c
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)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../../mcx/mcxw/linker.ld CACHE INTERNAL "")
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zephyr_linker_sources_ifdef(CONFIG_BT RAM_SECTIONS ../../mcx/mcxw/sections.ld)

‎soc/nxp/kinetis/kw45/Kconfig

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# KW45 Series
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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_KINETIS_KW45
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select ARM
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select CPU_CORTEX_M33
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select CPU_CORTEX_M_HAS_DWT
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select HAS_MCUX
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select CLOCK_CONTROL
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select SOC_RESET_HOOK
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select SOC_EARLY_INIT_HOOK
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config SOC_KW45B41Z83
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_FPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select ARMV8_M_DSP
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rsource "../../common/Kconfig.nbu"

‎soc/nxp/kinetis/kw45/Kconfig.defconfig

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# KW45 series configuration options
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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_KINETIS_KW45
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 96000000 if CORTEX_M_SYSTICK
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config MCUX_FLASH_K4_API
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default y
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config WDOG_INIT
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default n
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config SOC_SERIES
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default "kw45"
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config NUM_IRQS
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default 74
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if BT
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# Include intercore messaging component
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config NXP_RF_IMU
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default y
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# Set the controller's public identity using NXP vendor command
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config BT_HCI_SET_PUBLIC_ADDR
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default y
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# HCI RX buffers are received in ISR context. RX messages
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# need to be queued and processed by a dedicated thread
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config HCI_NXP_RX_THREAD
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default y
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endif # BT
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config PM
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select COUNTER
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config FLASH
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default y if BT
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config BT_BUF_EVT_DISCARDABLE_SIZE
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default 84 if BT
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choice LIBC_IMPLEMENTATION
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default NEWLIB_LIBC if PM
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endchoice
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endif # SOC_SERIES_KINETIS_KW45

‎soc/nxp/kinetis/kw45/Kconfig.soc

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# KW45 Series
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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_KINETIS_KW45
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bool
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select SOC_FAMILY_KINETIS
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config SOC_SERIES
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default "kw45" if SOC_SERIES_KINETIS_KW45
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config SOC_KW45B41Z83
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bool
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select SOC_SERIES_KINETIS_KW45
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config SOC
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default "kw45b41z83" if SOC_KW45B41Z83
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config SOC_PART_NUMBER_KW45B41Z83AFTA
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bool
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config SOC_PART_NUMBER
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default "KW45B41Z83AFTA" if SOC_PART_NUMBER_KW45B41Z83AFTA

‎soc/nxp/kinetis/kw45/power.c

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/pm/pm.h>
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#include <zephyr/timeout_q.h>
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include "fsl_pm_core.h"
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#include "fsl_pm_board.h"
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#include "fwk_platform_lowpower.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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#define LPTMR0_DEV DT_NODELABEL(lptmr0)
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const struct device *const counter_dev = DEVICE_DT_GET(LPTMR0_DEV);
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/* TODO: change this line when PowerDown is enabled
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* This definition is needed for compilation, but only used on PowerDown
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*/
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uint32_t m_warmboot_stack_end __section("RetainedMem");
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/* -------------------------------------------------------------------------- */
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/* Private variables */
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/* -------------------------------------------------------------------------- */
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static pm_handle_t pm_hdl;
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static bool unsupported_state;
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static uint8_t lowest_state;
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/* -------------------------------------------------------------------------- */
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/* Public functions */
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/* -------------------------------------------------------------------------- */
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__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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int32_t timeout_expiry;
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struct counter_top_cfg counter_info;
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ARG_UNUSED(substate_id);
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__ASSERT(device_is_ready(counter_dev), "ERROR: Counter is not ready to be used");
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__disable_irq();
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irq_unlock(0);
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unsupported_state = false;
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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lowest_state = PM_LP_STATE_DEEP_SLEEP;
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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unsupported_state = true;
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break;
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}
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if (!unsupported_state) {
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if (PM_SetConstraints(lowest_state, 0) != 0) {
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__ASSERT(0, "ERROR: to set constraint");
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}
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timeout_expiry = z_get_next_timeout_expiry();
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counter_info.ticks =
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counter_us_to_ticks(counter_dev, k_ticks_to_us_floor32(timeout_expiry));
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counter_info.callback = NULL;
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counter_info.user_data = NULL;
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counter_set_top_value(counter_dev, &counter_info);
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/* Disable systick before going to low power */
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SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
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/* LPTMR (counter) is set to wakeup the system after the requested time */
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if (counter_start(counter_dev) != 0) {
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__ASSERT(0, "ERROR: can't start timer to wakeup");
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}
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PM_EnterLowPower(k_ticks_to_us_floor64(timeout_expiry));
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}
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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uint32_t slept_time_ticks;
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uint32_t slept_time_us;
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ARG_UNUSED(state);
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ARG_UNUSED(substate_id);
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if (!unsupported_state) {
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counter_get_value(counter_dev, &slept_time_ticks);
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/* Reactivate systick */
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SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
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counter_stop(counter_dev);
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slept_time_us = counter_ticks_to_us(counter_dev, slept_time_ticks);
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/* Announce the time slept to the kernel*/
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sys_clock_announce(k_us_to_ticks_near32(slept_time_us));
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if (PM_ReleaseConstraints(lowest_state, 0) != 0) {
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__ASSERT(0, "ERROR: to release constraint");
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}
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}
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/* Clear PRIMASK */
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__enable_irq();
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}
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static int kw45_power_init(void)
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{
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int ret = 0;
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PM_CreateHandle(&pm_hdl);
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PM_EnablePowerManager(true);
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PLATFORM_LowPowerInit();
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#if !defined(CONFIG_BT)
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RFMC->CTRL |= RFMC_CTRL_RFMC_RST(0x1U);
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RFMC->CTRL &= ~RFMC_CTRL_RFMC_RST_MASK;
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/* NBU was probably in low power before the RFMC reset, so we need to wait for
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* the FRO clock to be valid before accessing RF_CMC
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*/
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while ((RFMC->RF2P4GHZ_STAT & RFMC_RF2P4GHZ_STAT_FRO_CLK_VLD_STAT_MASK) == 0U) {
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;
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}
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RF_CMC1->RADIO_LP |= RF_CMC1_RADIO_LP_CK(0x2);
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/* Force low power entry request to the radio domain */
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RFMC->RF2P4GHZ_CTRL |= RFMC_RF2P4GHZ_CTRL_LP_ENTER(0x1U);
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#endif
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return ret;
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}
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SYS_INIT(kw45_power_init, PRE_KERNEL_2, 0);

‎soc/nxp/kinetis/soc.yml

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- name: mke15z7
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- name: mke17z7
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- name: mke17z9
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- name: kw45
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socs:
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- name: kw45b41z83
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runners:
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run_once:
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'--erase':

‎west.yml

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groups:
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- hal
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- name: hal_nxp
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revision: be4d59d9c84e9519f3c05645f410b6dd63aeac4f
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revision: pull/502/head
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path: modules/hal/nxp
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groups:
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- hal

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