soc: wch: Reorganize Qingke V4 Socs for future

Reorganization for deduplication.

Signed-off-by: Camille BAUD <mail@massdriver.space>

Author: VynDragon

drivers/clock_control/clock_control_wch_rcc.c

@@ -90,7 +90,7 @@ static void clock_control_wch_rcc_setup_flash(void)
 	} else {
 		latency = FLASH_ACTLR_LATENCY_1;
 	}
-#elif defined(CONFIG_SOC_SERIES_CH32V00X)
+#elif defined(CONFIG_SOC_SERIES_QINGKE_V2A)
 	if (WCH_RCC_SYSCLK <= 15000000) {
 		latency = FLASH_ACTLR_LATENCY_0;
 	} else if (WCH_RCC_SYSCLK <= 24000000) {

drivers/timer/Kconfig.wch_ch32v00x

@@ -3,6 +3,6 @@
 
 config CH32V00X_SYSTICK
 	bool "CH32V QingKe core systick timer"
-	depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C || SOC_SERIES_CH32V00X
+	depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4
 	default y
 	depends on DT_HAS_WCH_SYSTICK_ENABLED

modules/hal_wch/ch32fun.h

@@ -7,18 +7,14 @@
 #ifndef _CH32FUN_H
 #define _CH32FUN_H
 
-#if defined(CONFIG_SOC_CH32V003)
+#if defined(CONFIG_SOC_CH32V003) || defined(CONFIG_SOC_CH32V006)
 #define CH32V003 1
 #include <ch32v003fun.h>
 #endif
 
-#if defined(CONFIG_SOC_SERIES_CH32V00X)
-#define CH32V003 1
-#include <ch32v003fun.h>
-#endif
-
-#if defined(CONFIG_SOC_SERIES_QINGKE_V4C)
+#if defined(CONFIG_SOC_CH32V208)
 #define CH32V20x 1
+#define CH32V20x_D8W 1
 #include <ch32v003fun.h>
 #endif
 

soc/wch/ch32v/ch32v00x/Kconfig

@@ -6,3 +6,4 @@ config SOC_SERIES_QINGKE_V2A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZMMUL

soc/wch/ch32v/ch32v00x/Kconfig.defconfig

@@ -1,20 +1,11 @@
-# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024-2025 Michael Hope
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_QINGKE_V2A
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
 
-config MAIN_STACK_SIZE
-	default 512
-
-config IDLE_STACK_SIZE
-	default 256
-
-config ISR_STACK_SIZE
-	default 256
-
 config CLOCK_CONTROL
 	default y