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boards: ruiside: RA8D1 Vision Board: add support
this is another board from ruiside, tested uart, button, led, sdram, sd card Signed-off-by: Shan Pen <bricle031@gmail.com>
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‎boards/ruiside/ra8d1_vision_board/Kconfig.defconfig

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# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_RA8D1_VISION_BOARD
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if DISK_DRIVER_SDMMC
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config SD_CMD_TIMEOUT
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default 1000
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endif # DISK_DRIVER_SDMMC
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endif # BOARD_RA8D1_VISION_BOARD

‎boards/ruiside/ra8d1_vision_board/Kconfig.ra8d1_vision_board

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# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_RA8D1_VISION_BOARD
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select SOC_R7FA8D1BHECBD

‎boards/ruiside/ra8d1_vision_board/board.cmake

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# SPDX-License-Identifier: Apache-2.0
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# keep first
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board_runner_args(pyocd "--target=R7FA8D1BH")
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# keep first
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include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

‎boards/ruiside/ra8d1_vision_board/board.yml

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board:
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name: ra8d1_vision_board
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full_name: RA8D1 Vision Board
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vendor: ruiside
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socs:
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- name: r7fa8d1bhecbd

‎boards/ruiside/ra8d1_vision_board/doc/index.rst

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.. zephyr:board:: ra8d1_vision_board
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Overview
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********
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The RA8D1-VISION-BOARD, based on the Renesas Cortex-M85 architecture RA8D1 chip, offers
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engineers a flexible and comprehensive development platform, empowering them to explore the realm of
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machine vision more deeply.
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Key Features
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- Arm Cortex-M85
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- 480MHz frequency, on-chip 2Mb Flash, 1Mb SRAM
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- 32Mb-SDRAM; 8Mb-QSPI Flash
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- MIPI-DSI; RGB666; 8bit Camera
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- On-board DAP-LINK debugger with CMSIS-DAP
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- Raspberry Pi Interface
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More information about the board can be found at the `RA8D1-VISION-BOARD website`_.
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Hardware
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********
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Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_
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Supported Features
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==================
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.. zephyr:board-supported-hw::
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Default Zephyr Peripheral Mapping:
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----------------------------------
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The RA8D1-VISION-BOARD board features a On-board CMSIS-DAP debugger/programmer. Board is configured as follows:
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- UART9 TX/RX : P209/P208 (CMSIS-DAP Virtual Port Com)
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- LED0 : P102
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- LED1 : P106
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- LED2 : PA07
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- USER BUTTON : P907
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Programming and Debugging
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*************************
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.. zephyr:board-supported-runners::
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Applications for the ``ra8d1_vision_board`` board can be
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built, flashed, and debugged in the usual way. See
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:ref:`build_an_application` and :ref:`application_run` for more details on
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building and running.
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**Note:** Only support from SDK v0.16.6 in which GCC for Cortex Arm-M85 was available.
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To build for RA8D1-VISION-BOARD user need to get and install GNU Arm Embedded toolchain from https://github.com/zephyrproject-rtos/sdk-ng/releases/tag/v0.16.6
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Flashing
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========
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Program can be flashed to RA8D1-VISION-BOARD via the on-board DAP-LINK debugger.
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Linux users: to fix the permission issue, simply add the following udev rule for the
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CMSIS-DAP interface:
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.. code-block:: console
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$ echo 'SUBSYSTEM=="usb", ATTR{idVendor}=="0416", ATTR{idProduct}=="7687", MODE:="666"' > /etc/udev/rules.d/50-cmsis-dap.rules
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To flash the program to board
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1. Connect to DAP-LINK via USB port to host PC
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2. Execute west command
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.. code-block:: console
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west flash
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Debugging
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=========
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You can debug an application in the usual way. Here is an example for the
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:zephyr:code-sample:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: ra8d1_vision_board
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:maybe-skip-config:
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:goals: debug
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References
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**********
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.. target-notes::
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.. _RA8D1-VISION-BOARD Website:
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https://github.com/RT-Thread-Studio/sdk-bsp-ra8d1-vision-board
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.. _RA8D1 Group User's Manual Hardware:
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https://www.renesas.com/us/en/document/mah/ra8d1-group-users-manual-hardware

‎boards/ruiside/ra8d1_vision_board/doc/ra8d1_vision_board.webp

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‎boards/ruiside/ra8d1_vision_board/ra8d1_vision_board-pinctrl.dtsi

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/*
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* Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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sci9_default: sci9_default {
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group1 {
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/* tx */
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psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 9)>;
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drive-strength = "medium";
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};
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group2 {
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/* rx */
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psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 8)>;
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};
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};
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sdram_default: sdram_default {
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group1 {
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/* SDRAM_DQM1 */
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psels = <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
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/* SDRAM_CKE */
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<RA_PSEL(RA_PSEL_BUS, 1, 13)>,
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/* SDRAM_WE */
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<RA_PSEL(RA_PSEL_BUS, 1, 14)>,
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/* SDRAM_CS */
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<RA_PSEL(RA_PSEL_BUS, 1, 15)>,
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/* SDRAM_A0 */
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<RA_PSEL(RA_PSEL_BUS, 3, 0)>,
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/* SDRAM_A1 */
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<RA_PSEL(RA_PSEL_BUS, 3, 1)>,
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/* SDRAM_A2 */
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<RA_PSEL(RA_PSEL_BUS, 3, 2)>,
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/* SDRAM_A3 */
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<RA_PSEL(RA_PSEL_BUS, 3, 3)>,
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/* SDRAM_A4 */
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<RA_PSEL(RA_PSEL_BUS, 3, 4)>,
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/* SDRAM_A5 */
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<RA_PSEL(RA_PSEL_BUS, 3, 5)>,
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/* SDRAM_A6 */
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<RA_PSEL(RA_PSEL_BUS, 3, 6)>,
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/* SDRAM_A7 */
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<RA_PSEL(RA_PSEL_BUS, 3, 7)>,
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/* SDRAM_A8 */
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<RA_PSEL(RA_PSEL_BUS, 3, 8)>,
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/* SDRAM_A9 */
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<RA_PSEL(RA_PSEL_BUS, 3, 9)>,
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/* SDRAM_A10 */
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<RA_PSEL(RA_PSEL_BUS, 3, 10)>,
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/* SDRAM_A11 */
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<RA_PSEL(RA_PSEL_BUS, 3, 11)>,
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/* SDRAM_A12 */
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<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
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/* SDRAM_A13 */
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<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
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/* SDRAM_A14 */
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<RA_PSEL(RA_PSEL_BUS, 9, 5)>,
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/* SDRAM_A15 */
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<RA_PSEL(RA_PSEL_BUS, 9, 6)>,
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/* SDRAM_D0 */
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<RA_PSEL(RA_PSEL_BUS, 6, 1)>,
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/* SDRAM_D1 */
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<RA_PSEL(RA_PSEL_BUS, 6, 2)>,
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/* SDRAM_D2 */
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<RA_PSEL(RA_PSEL_BUS, 6, 3)>,
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/* SDRAM_D3 */
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<RA_PSEL(RA_PSEL_BUS, 6, 4)>,
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/* SDRAM_D4 */
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<RA_PSEL(RA_PSEL_BUS, 6, 5)>,
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/* SDRAM_D5 */
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<RA_PSEL(RA_PSEL_BUS, 6, 6)>,
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/* SDRAM_D6 */
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<RA_PSEL(RA_PSEL_BUS, 6, 7)>,
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/* SDRAM_D8 */
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<RA_PSEL(RA_PSEL_BUS, 6, 9)>,
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/* SDRAM_D9 */
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<RA_PSEL(RA_PSEL_BUS, 6, 10)>,
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/* SDRAM_D10 */
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<RA_PSEL(RA_PSEL_BUS, 6, 11)>,
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/* SDRAM_D11 */
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<RA_PSEL(RA_PSEL_BUS, 6, 12)>,
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/* SDRAM_D12 */
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<RA_PSEL(RA_PSEL_BUS, 6, 13)>,
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/* SDRAM_D13 */
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<RA_PSEL(RA_PSEL_BUS, 6, 14)>,
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/* SDRAM_D14 */
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<RA_PSEL(RA_PSEL_BUS, 6, 15)>,
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/* SDRAM_RAS */
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<RA_PSEL(RA_PSEL_BUS, 9, 8)>,
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/* SDRAM_CAS */
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<RA_PSEL(RA_PSEL_BUS, 9, 9)>;
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drive-strength = "high";
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};
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group2 {
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/* SDRAM_SDCLK */
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psels = <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
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drive-strength = "highspeed-high";
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};
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group3 {
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/* SDRAM_D7 */
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psels = <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
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/* SDRAM_D15 */
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<RA_PSEL(RA_PSEL_BUS, 10, 8)>,
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/* SDRAM_DQM0 */
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<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
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drive-strength = "high";
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};
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};
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sdhc1_default: sdhc1_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_SDHI, 5, 3)>, /* SDCD */
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<RA_PSEL(RA_PSEL_SDHI, 8, 11)>, /* SDCMD */
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<RA_PSEL(RA_PSEL_SDHI, 8, 12)>, /* SDDATA0 */
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<RA_PSEL(RA_PSEL_SDHI, 5, 0)>, /* SDDATA1 */
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<RA_PSEL(RA_PSEL_SDHI, 5, 1)>, /* SDDATA2 */
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<RA_PSEL(RA_PSEL_SDHI, 5, 2)>; /* SDDATA3 */
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drive-strength = "high";
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};
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group2 {
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psels = <RA_PSEL(RA_PSEL_SDHI, 8, 10)>; /* SDCLK */
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drive-strength = "highspeed-high";
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};
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};
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};

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