arch: microblaze: add MicroBlaze to arch/KConfig

Internal references: FWRIVERHD-4554

Signed-off-by: Alp Sayin <alpsayin@gmail.com>

Author: alpsayin

arch/Kconfig

@@ -104,6 +104,18 @@ config NIOS2
 	help
 	  Nios II Gen 2 architecture
 
+config MICROBLAZE
+	bool
+	select ARCH_IS_SET
+	select ATOMIC_OPERATIONS_C
+	select HAS_DTS
+	select GEN_ISR_TABLES
+	select GEN_SW_ISR_TABLE
+	imply DYNAMIC_INTERRUPTS
+	imply ARCH_HAS_CUSTOM_BUSY_WAIT
+	help
+	  MicroBlaze architecture
+
 config RISCV
 	bool
 	select ARCH_IS_SET

arch/microblaze/Kconfig

@@ -0,0 +1,102 @@
+# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
+# Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+
+menu "MicroBlaze Options"
+	depends on MICROBLAZE
+
+config ARCH
+	def_string "microblaze"
+
+config CPU_MICROBLAZE
+	def_bool y
+	select ARCH_HAS_EXTRA_EXCEPTION_INFO
+	help
+		This option signifies the use of a MicroBlaze CPU
+
+config CPU_VERSION
+	prompt "MicroBlaze CPU Version"
+	def_string "v9.00.a"
+	help
+		Use features of, and schedule code for, the given CPU.
+		Supported values are in the format "vX.YY.Z",
+		where X is a major version, YY is the minor version, and Z is compatibility code.
+		Example values are "v3.00.a", "v4.00.b", "v5.00.a", "v5.00.b", "v6.00.a".
+		Taken from https://gcc.gnu.org/onlinedocs/gcc/MicroBlaze-Options.html
+
+config GEN_IRQ_VECTOR_TABLE
+	bool
+	default n if MICROBLAZE
+	help
+		MicroBlaze has a single interrupt and therefore doesn't have an IRQ vector table.
+
+config BIG_ENDIAN
+	bool
+	default n if MICROBLAZE
+	help
+		Our current default endianness is Little-endian.
+
+config ARCH_SW_ISR_TABLE_ALIGN
+	prompt "SW_ISR Table Align Size"
+	default 4
+
+config NUM_IRQS
+	def_int 1
+	help
+		This isn't really a choice either because a barebones MicroBlaze offers
+		only 1 external interrupt pin (which is usually connected to an Xlnx Intc
+		or probably a single peripheral which a user wants IRQs from).
+
+choice
+	prompt "Idle Sleep Option"
+	default MICROBLAZE_IDLE_NOP
+
+	config MICROBLAZE_IDLE_NOP
+		bool "NOP (no power saving)"
+		help
+			Executes pseudo-assembly instruction nop in idle.
+			Reset_Mode[0:1] is set to 10
+
+	config MICROBLAZE_IDLE_SLEEP
+		bool "Sleep"
+		help
+			Executes pseudo-assembly instruction sleep in idle.
+			Reset_Mode[0:1] is set to 10
+
+	config MICROBLAZE_IDLE_HIBERNATE
+		bool "Hibernate"
+		help
+			Executes pseudo-assembly instruction hibernate in idle.
+
+	config MICROBLAZE_IDLE_SUSPEND
+		bool "Suspend"
+		help
+			Executes pseudo-assembly instruction suspend in idle.
+endchoice
+
+config MICROBLAZE_DUMP_ON_EXCEPTION
+	bool "Dump core on exceptions"
+	default y
+
+# Bump the kernel default stack size values.
+config MAIN_STACK_SIZE
+	default 4096 if COVERAGE_GCOV
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024
+
+config ISR_STACK_SIZE
+	default 4096
+
+config TEST_EXTRA_STACK_SIZE
+	default 4096 if COVERAGE_GCOV
+	default 2048
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 4096
+
+source "arch/microblaze/Kconfig.features"
+
+endmenu

arch/microblaze/Kconfig.features

@@ -0,0 +1,69 @@
+# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
+# Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+
+menu "HW Feature Options"
+	depends on MICROBLAZE
+
+config MICROBLAZE_USE_MSR_INSTR
+	prompt "Use msrset & msrclr instructions"
+	def_bool y
+	help
+		This depends on CPU supporting msrset/msrclr instructions.
+		xparameters would define this as USE_MSR_INSTR = 1.
+
+config USE_BARREL_SHIFT_INSTR
+	prompt "Use barrel shift instructions"
+	def_bool y
+	help
+		This depends on CPU supporting barrel shift instructions.
+		xparameters would define this as USE_BARREL = 1.
+
+config USE_PATTERN_COMPARE_INSTR
+	prompt "Use pattern compare instructions"
+	def_bool y
+	help
+		This depends on CPU supporting pattern compare instructions.
+		xparameters would define this as USE_PCMP = 1.
+
+config USE_DIV_INSTR
+	prompt "Use division instructions"
+	def_bool y
+	help
+		This depends on CPU supporting hardware division instructions.
+		xparameters would define this as USE_DIV = 1.
+
+config USE_MUL_INSTR
+	prompt "Use multiplication instructions"
+	def_bool y
+	help
+		This depends on CPU supporting hardware multiplication instructions.
+		xparameters would define this as USE_HW_MUL >= 1.
+
+config USE_MULHI_INSTR
+	prompt "Use mulhi for multiplication of higher bits"
+	def_bool y
+	depends on USE_MUL_INSTR
+	help
+		Use multiply high instructions for high part of 32x32 multiply.
+		This depends on CPU supporting hardware high multiplication instructions.
+		xparameters would define this as USE_HW_MUL = 2.
+
+config USE_HARDWARE_FLOAT_INSTR
+	def_bool n
+	depends on CPU_HAS_FPU
+	help
+		This depends on CPU supporting hardware float instructions.
+		xparameters would define this as USE_FPU = 1.
+
+config DATA_IS_TEXT_RELATIVE
+	bool "Assume data & text segment distance is static"
+	default y
+	help
+		Assume that the displacement between the text and data segments is fixed at
+		static link time. This allows data to be referenced by offset from start of
+		text address instead of GOT (r20) since PC-relative addressing is not supported.
+		Injects -mpic-data-is-text-relative
+
+endmenu