drivers: clock_control: clock_control_max32: Enable IPLL

Make enabling MAX78002 IPLL clock from dts possible

Signed-off-by: Mikolaj Klikowicz <mklikowicz@antmicro.com>

Author: mikolaj-klikowicz

drivers/clock_control/clock_control_max32.c

@@ -85,6 +85,9 @@ static int api_get_rate(const struct device *dev, clock_control_subsys_t clkcfg,
 	case ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8:
 		*rate = ADI_MAX32_CLK_IBRO_FREQ / 8;
 		break;
+	case ADI_MAX32_PRPH_CLK_SRC_IPLL:
+		*rate = ADI_MAX32_CLK_IPLL_FREQ;
+		break;
 	default:
 		*rate = 0U;
 		/* Invalid parameters */
@@ -130,6 +133,10 @@ static void setup_fixed_clocks(void)
 	MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_ERTCO);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk_ipll))
+	MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_IPLL);
+#endif
+
 /* Some device does not support external clock */
 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_extclk), fixed_clock, okay)
 	MXC_SYS_ClockSourceEnable(ADI_MAX32_CLK_EXTCLK);