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VynDragonVynDragon
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drivers: Add header file with common functions for BFLB
This moves the couple functions that are and will be all over the various clock operations for all platforms. Signed-off-by: Camille BAUD <mail@massdriver.space>
1 parent c906d4a commit 8c38b85

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3 files changed

+64
-73
lines changed

3 files changed

+64
-73
lines changed

‎drivers/clock_control/clock_control_bl60x.c

Lines changed: 19 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(clock_control_bl60x, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
2121
#include <bouffalolab/bl60x/pds_reg.h>
2222
#include <bouffalolab/bl60x/l1c_reg.h>
2323
#include <bouffalolab/bl60x/extra_defines.h>
24+
#include <zephyr/drivers/clock_control/clock_control_bflb_common.h>
2425

2526
#define CLK_SRC_IS(clk, src) \
2627
DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
@@ -89,31 +90,6 @@ const static uint32_t clock_control_bl60x_crystal_SDMIN_table[5] = {
8990
0x49D39D,
9091
};
9192

92-
static inline void clock_control_bl60x_clock_settle(void)
93-
{
94-
__asm__ volatile(".rept 15 ; nop ; .endr");
95-
}
96-
97-
/* 32 Mhz Oscillator: 0
98-
* crystal: 1
99-
* PLL and 32M: 2
100-
* PLL and crystal: 3
101-
*/
102-
static void clock_control_bl60x_set_root_clock(uint32_t clock)
103-
{
104-
uint32_t tmp;
105-
106-
/* invalid value, fallback to internal 32M */
107-
if (clock > 3) {
108-
clock = 0;
109-
}
110-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
111-
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
112-
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
113-
114-
clock_control_bl60x_clock_settle();
115-
}
116-
11793
static uint32_t clock_control_bl60x_get_root_clock(void)
11894
{
11995
uint32_t tmp;
@@ -132,7 +108,7 @@ static int clock_control_bl60x_deinit_crystal(void)
132108
tmp = tmp & AON_PU_XTAL_BUF_AON_UMSK;
133109
sys_write32(tmp, AON_BASE + AON_RF_TOP_AON_OFFSET);
134110

135-
clock_control_bl60x_clock_settle();
111+
clock_bflb_settle();
136112
return 0;
137113
}
138114

@@ -149,12 +125,12 @@ static int clock_control_bl60x_init_crystal(void)
149125

150126
/* wait for crystal to be powered on */
151127
do {
152-
clock_control_bl60x_clock_settle();
128+
clock_bflb_settle();
153129
tmp = sys_read32(AON_BASE + AON_TSEN_OFFSET);
154130
count--;
155131
} while (!(tmp & AON_XTAL_RDY_MSK) && count > 0);
156132

157-
clock_control_bl60x_clock_settle();
133+
clock_bflb_settle();
158134
if (count < 1) {
159135
return -1;
160136
}
@@ -171,7 +147,7 @@ static int clock_control_bl60x_set_root_clock_dividers(uint32_t hclk_div, uint32
171147

172148
/* security RC32M */
173149
if (old_rootclk > 1) {
174-
clock_control_bl60x_set_root_clock(0);
150+
clock_bflb_set_root_clock(0);
175151
}
176152

177153
/* set dividers */
@@ -186,16 +162,16 @@ static int clock_control_bl60x_set_root_clock_dividers(uint32_t hclk_div, uint32
186162
sys_write32(0x00000001, 0x40000FFC);
187163
sys_write32(0x00000000, 0x40000FFC);
188164

189-
clock_control_bl60x_clock_settle();
165+
clock_bflb_settle();
190166

191167
/* enable clocks */
192168
tmp = sys_read32(GLB_BASE + GLB_CLK_CFG0_OFFSET);
193169
tmp = (tmp & GLB_REG_BCLK_EN_UMSK) | (1U << GLB_REG_BCLK_EN_POS);
194170
tmp = (tmp & GLB_REG_HCLK_EN_UMSK) | (1U << GLB_REG_HCLK_EN_POS);
195171
sys_write32(tmp, GLB_BASE + GLB_CLK_CFG0_OFFSET);
196172

197-
clock_control_bl60x_set_root_clock(old_rootclk);
198-
clock_control_bl60x_clock_settle();
173+
clock_bflb_set_root_clock(old_rootclk);
174+
clock_bflb_settle();
199175

200176
return 0;
201177
}
@@ -288,7 +264,7 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
288264

289265
/* security RC32M */
290266
if (old_rootclk > 1) {
291-
clock_control_bl60x_set_root_clock(0);
267+
clock_bflb_set_root_clock(0);
292268
}
293269

294270
clock_control_bl60x_deinit_pll();
@@ -356,7 +332,7 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
356332
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
357333
tmp = (tmp & PDS_PU_CLKPLL_SFREG_UMSK) | (1U << PDS_PU_CLKPLL_SFREG_POS);
358334
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
359-
clock_control_bl60x_clock_settle();
335+
clock_bflb_settle();
360336

361337
/* enable PPL clock actual? */
362338
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
@@ -371,7 +347,7 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
371347
tmp = (tmp & PDS_CLKPLL_PU_POSTDIV_UMSK) | (1U << PDS_CLKPLL_PU_POSTDIV_POS);
372348
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
373349

374-
clock_control_bl60x_clock_settle();
350+
clock_bflb_settle();
375351

376352
/* reset couple things one by one? */
377353
tmp = sys_read32(PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
@@ -390,8 +366,8 @@ static void clock_control_bl60x_init_pll(enum bl60x_clkid source, uint32_t cryst
390366
tmp = (tmp & PDS_CLKPLL_SDM_RESET_UMSK) | (0U << PDS_CLKPLL_SDM_RESET_POS);
391367
sys_write32(tmp, PDS_BASE + PDS_PU_RST_CLKPLL_OFFSET);
392368

393-
clock_control_bl60x_set_root_clock(old_rootclk);
394-
clock_control_bl60x_clock_settle();
369+
clock_bflb_set_root_clock(old_rootclk);
370+
clock_bflb_settle();
395371
}
396372

397373
/*
@@ -439,7 +415,7 @@ static int clock_control_bl60x_clock_trim_32M(void)
439415
tmp = (tmp & PDS_RC32M_CODE_FR_EXT_UMSK) | trim << PDS_RC32M_CODE_FR_EXT_POS;
440416
sys_write32(tmp, PDS_BASE + PDS_RC32M_CTRL0_OFFSET);
441417

442-
clock_control_bl60x_clock_settle();
418+
clock_bflb_settle();
443419

444420
return 0;
445421
}
@@ -557,9 +533,9 @@ static void clock_control_bl60x_init_root_as_pll(const struct device *dev)
557533
clock_control_bl60x_select_PLL(data->root.pll_select);
558534

559535
if (data->pll.source == bl60x_clkid_clk_crystal) {
560-
clock_control_bl60x_set_root_clock(3);
536+
clock_bflb_set_root_clock(3);
561537
} else {
562-
clock_control_bl60x_set_root_clock(2);
538+
clock_bflb_set_root_clock(2);
563539
}
564540

565541
if (clock_control_bl60x_get_clk(dev) > MHZ(120)) {
@@ -572,7 +548,7 @@ static void clock_control_bl60x_init_root_as_pll(const struct device *dev)
572548

573549
static void clock_control_bl60x_init_root_as_crystal(const struct device *dev)
574550
{
575-
clock_control_bl60x_set_root_clock(1);
551+
clock_bflb_set_root_clock(1);
576552
sys_write32(clock_control_bl60x_get_clk(dev), CORECLOCKREGISTER);
577553
}
578554

@@ -590,7 +566,7 @@ static int clock_control_bl60x_update_root(const struct device *dev)
590566
sys_write32(tmp, GLB_BASE + GLB_CLK_CFG0_OFFSET);
591567

592568
/* set root clock to internal 32MHz Oscillator as failsafe */
593-
clock_control_bl60x_set_root_clock(0);
569+
clock_bflb_set_root_clock(0);
594570
if (clock_control_bl60x_set_root_clock_dividers(0, 0) != 0) {
595571
return -EIO;
596572
}
@@ -627,7 +603,7 @@ static int clock_control_bl60x_update_root(const struct device *dev)
627603
clock_control_bl60x_set_machine_timer_clock(
628604
1, 0, clock_control_bl60x_mtimer_get_clk_src_div(dev));
629605

630-
clock_control_bl60x_clock_settle();
606+
clock_bflb_settle();
631607

632608
return ret;
633609
}

‎drivers/syscon/syscon_bflb_efuse.c

Lines changed: 6 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ LOG_MODULE_REGISTER(efuse_bflb, CONFIG_SYSCON_LOG_LEVEL);
1616
#include <bouffalolab/bl60x/hbn_reg.h>
1717
#include <bouffalolab/bl60x/ef_ctrl_reg.h>
1818
#include <bouffalolab/bl60x/extra_defines.h>
19+
#include <zephyr/drivers/clock_control/clock_control_bflb_common.h>
1920

2021
struct efuse_bflb_data {
2122
uint8_t cache[DT_INST_PROP(0, size)];
@@ -27,31 +28,6 @@ struct efuse_bflb_config {
2728
size_t size;
2829
};
2930

30-
static inline void efuse_bflb_clock_settle(void)
31-
{
32-
__asm__ volatile (".rept 15 ; nop ; .endr");
33-
}
34-
35-
/* 32 Mhz Oscillator: 0
36-
* crystal: 1
37-
* PLL and 32M: 2
38-
* PLL and crystal: 3
39-
*/
40-
static void efuse_bflb_set_root_clock(uint32_t clock)
41-
{
42-
uint32_t tmp;
43-
44-
/* invalid value, fallback to internal 32M */
45-
if (clock > 3) {
46-
clock = 0;
47-
}
48-
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
49-
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
50-
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
51-
52-
efuse_bflb_clock_settle();
53-
}
54-
5531
static void efuse_bflb_clock_delay_32M_ms(uint32_t ms)
5632
{
5733
uint32_t count = 0;
@@ -107,7 +83,7 @@ static void efuse_bflb_efuse_read(const struct device *dev)
10783
| (0 << EF_CTRL_EF_IF_0_TRIG_POS);
10884

10985
sys_write32(tmp, config->addr + EF_CTRL_EF_IF_CTRL_0_OFFSET);
110-
efuse_bflb_clock_settle();
86+
clock_bflb_settle();
11187

11288
/* clear PDS cache registry */
11389
for (uint32_t i = 0; i < config->size / 4; i++) {
@@ -177,8 +153,8 @@ static void efuse_bflb_cache(const struct device *dev)
177153
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
178154
old_clock_root = (tmp & HBN_ROOT_CLK_SEL_MSK) >> HBN_ROOT_CLK_SEL_POS;
179155

180-
efuse_bflb_set_root_clock(0);
181-
efuse_bflb_clock_settle();
156+
clock_bflb_set_root_clock(0);
157+
clock_bflb_settle();
182158

183159
efuse_bflb_efuse_read(dev);
184160
/* reads *must* be 32-bits aligned AND does not work with the method memcpy uses */
@@ -190,8 +166,8 @@ static void efuse_bflb_cache(const struct device *dev)
190166
data->cache[i * sizeof(uint32_t) + 0] = (tmp & 0x000000FFU);
191167
}
192168

193-
efuse_bflb_set_root_clock(old_clock_root);
194-
efuse_bflb_clock_settle();
169+
clock_bflb_set_root_clock(old_clock_root);
170+
clock_bflb_settle();
195171
data->cached = true;
196172
}
197173

‎include/zephyr/drivers/clock_control/clock_control_bflb_common.h

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
/*
2+
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/* Contains short functions relevant to timing and clocks common to all Bouffalolab platforms */
8+
9+
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
10+
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_
11+
12+
/* Function that busy waits for a few cycles */
13+
static inline void clock_bflb_settle(void)
14+
{
15+
__asm__ volatile (".rept 20 ; nop ; .endr");
16+
}
17+
18+
/* Common main clock mux
19+
*
20+
* 32 Mhz Oscillator: 0 (using XCLK)
21+
* crystal: 1 (using XCLK)
22+
* PLL and 32M: 2 (using PLL mux, XCLK is 32M)
23+
* PLL and crystal: 3 (using PLL mux, XCLK is crystal)
24+
*/
25+
static inline void clock_bflb_set_root_clock(uint32_t clock)
26+
{
27+
uint32_t tmp;
28+
29+
/* invalid value, fallback to internal 32M */
30+
if (clock > 3) {
31+
clock = 0;
32+
}
33+
tmp = sys_read32(HBN_BASE + HBN_GLB_OFFSET);
34+
tmp = (tmp & HBN_ROOT_CLK_SEL_UMSK) | (clock << HBN_ROOT_CLK_SEL_POS);
35+
sys_write32(tmp, HBN_BASE + HBN_GLB_OFFSET);
36+
37+
clock_bflb_settle();
38+
}
39+
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_BFLB_COMMON_H_ */

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