drivers: spi: dw: support rx sample delay

The RX_SAMPLE_DELAY register controls the number of ssi_clk cycles that
are delayed from the default sample time before the actual sample of the
rxd input occurs. A 'rx-sample-delay' devicetree property is added to
support the delay control.

Signed-off-by: Younghyun Park <younghyunpark@google.com>

Author: myguitar

drivers/spi/spi_dw.c

@@ -423,6 +423,15 @@ static int transceive(const struct device *dev,
 	/* Rx Threshold */
 	write_rxftlr(dev, reg_data);
 
+	/* Rx sample delay */
+	if (info->rx_sample_delay) {
+		reg_data = read_rx_sample_dly(dev);
+		reg_data &= ~DW_SPI_RX_SAMPLE_DELAY_MASK;
+		reg_data |= FIELD_PREP(DW_SPI_RX_SAMPLE_DELAY_MASK,
+				       info->rx_sample_delay);
+		write_rx_sample_dly(dev, reg_data);
+	}
+
 	/* Enable interrupts */
 	reg_data = !rx_bufs ?
 		DW_SPI_IMR_UNMASK & DW_SPI_IMR_MASK_RX :
@@ -647,6 +656,7 @@ COND_CODE_1(IS_EQ(DT_NUM_IRQS(DT_DRV_INST(inst)), 1),              \
 		.serial_target = DT_INST_PROP(inst, serial_target),                         \
 		.fifo_depth = DT_INST_PROP(inst, fifo_depth),                               \
 		.max_xfer_size = DT_INST_PROP(inst, max_xfer_size),                         \
+		.rx_sample_delay = DT_INST_PROP(inst, rx_sample_delay),                     \
 		IF_ENABLED(CONFIG_PINCTRL, (.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),)) \
 		COND_CODE_1(DT_INST_PROP(inst, aux_reg),                                    \
 			(.read_func = aux_reg_read,                                         \

drivers/spi/spi_dw.h

@@ -35,6 +35,7 @@ struct spi_dw_config {
 	bool serial_target;
 	uint8_t fifo_depth;
 	uint8_t max_xfer_size;
+	uint8_t rx_sample_delay;
 #ifdef CONFIG_PINCTRL
 	const struct pinctrl_dev_config *pcfg;
 #endif
@@ -273,6 +274,9 @@ static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
 					   DW_SPI_IMR_RXOIM | \
 					   DW_SPI_IMR_RXFIM))
 
+/* RX Sample Delay */
+#define DW_SPI_RX_SAMPLE_DELAY_MASK	GENMASK(7, 0)
+
 /*
  * Including the right register definition file
  * SoC SPECIFIC!

drivers/spi/spi_dw_regs.h

@@ -51,6 +51,8 @@ DEFINE_MM_REG_READ(txftlr, DW_SPI_REG_TXFTLR, 32)
 DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
 DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
 DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
+DEFINE_MM_REG_WRITE(rx_sample_dly, DW_SPI_REG_RX_SAMPLE_DLY, 32)
+DEFINE_MM_REG_READ(rx_sample_dly, DW_SPI_REG_RX_SAMPLE_DLY, 32)
 
 #ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
 DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)

dts/bindings/spi/snps,designware-spi.yaml

@@ -44,3 +44,12 @@ properties:
     enum:
       - 16
       - 32
+
+  rx-sample-delay:
+    type: int
+    default: 0
+    description: |
+      Receive Data(rxd) Sample Delay. This is used to delay
+      the sample of the rxd input port. Each value represents
+      a single ssi_clk delay on the sample of rxd. Default is
+      0 and delay ranges from 0-255.