dts: arm: st: stm32mp25*_m33.dtsi: add init dtsi

Add the initial device tree source include (dtsi) files for the
stm32mp25 series boards, covering non-secure configuration for zephyr on
the Cortex-M33 core.
These files provide the basic hardware description, including CPU
(Cortex-M33), memory, RCC clock controller and NVIC interrupt
controller.

Key features:
- Set flash and RAM addresses to DDR memory.
- Adjust RCC peripheral address for non-secure context.

Signed-off-by: Youssef Zini <youssef.zini@savoirfairelinux.com>

Author: youssefz24

dts/arm/st/mp2/stm32mp251_m33.dtsi

@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp2/stm32mp2_m33.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32mp251", "st,stm32mp2", "simple-bus";
+	};
+};

dts/arm/st/mp2/stm32mp253_m33.dtsi

@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp2/stm32mp251_m33.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32mp253", "st,stm32mp2", "simple-bus";
+	};
+};

dts/arm/st/mp2/stm32mp255_m33.dtsi

@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp2/stm32mp253_m33.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32mp255", "st,stm32mp2", "simple-bus";
+	};
+};

dts/arm/st/mp2/stm32mp257_m33.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp2/stm32mp255_m33.dtsi>
+
+/ {
+	ddr_code: memory0@80100000 {
+		reg = <0x80100000 DT_SIZE_M(8)>;
+	};
+
+	ddr_sys: memory1@80a00000 {
+		reg = <0x80a00000 DT_SIZE_M(8)>;
+	};
+
+	soc {
+		compatible = "st,stm32mp257", "st,stm32mp2", "simple-bus";
+	};
+};

dts/arm/st/mp2/stm32mp2_m33.dtsi

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+		};
+	};
+
+	ddr_code: memory0@80100000 {
+		compatible = "mmio-sram";
+	};
+
+	ddr_sys: memory1@80a00000 {
+		compatible = "mmio-sram";
+	};
+
+	soc {
+		rcc: rcc@44200000  {
+			compatible = "st,stm32mp2-rcc";
+			clocks-controller;
+			#clock-cells = <2>;
+			reg = <0x44200000 DT_SIZE_K(64)>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};