Skip to content

Commit 86b3146

Browse files
dnltzkartben
dnltz
authored and
kartben
committed
drivers: serial: Add aesc UART driver
Add minimal support for the aesc silicon UART IP core. This core includes an internal clock divider and supports flexible frame configurations, allowing for variable data length, parity, and stop bit settings. The current driver version does not support interrupts. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
1 parent 3112f85 commit 86b3146

File tree

5 files changed

+159
-0
lines changed

5 files changed

+159
-0
lines changed

‎drivers/serial/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c
1717
zephyr_library_sources_ifdef(CONFIG_LEUART_GECKO leuart_gecko.c)
1818
zephyr_library_sources_ifdef(CONFIG_LPUART_ESP32 lpuart_esp32.c)
1919
zephyr_library_sources_ifdef(CONFIG_SERIAL_ESP32_USB serial_esp32_usb.c)
20+
zephyr_library_sources_ifdef(CONFIG_UART_AESC uart_aesc.c)
2021
zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
2122
zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)
2223
zephyr_library_sources_ifdef(CONFIG_UART_APBUART uart_apbuart.c)

‎drivers/serial/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ config UART_SHELL
157157
comment "Serial Drivers"
158158

159159
# zephyr-keep-sorted-start
160+
rsource "Kconfig.aesc"
160161
rsource "Kconfig.altera"
161162
rsource "Kconfig.altera_jtag"
162163
rsource "Kconfig.apbuart"

‎drivers/serial/Kconfig.aesc

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# Copyright (c) 2025 Aesc Silicon
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
config UART_AESC
5+
bool "Aesc Silicon UART driver"
6+
default y
7+
depends on DT_HAS_AESC_UART_ENABLED
8+
select SERIAL_HAS_DRIVER
9+
help
10+
Enable the Aesc Silicon UART driver.

‎drivers/serial/uart_aesc.c

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,126 @@
1+
/*
2+
* Copyright (c) 2025 Aesc Silicon
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#define DT_DRV_COMPAT aesc_uart
8+
9+
#include <errno.h>
10+
#include <ip_identification.h>
11+
#include <soc.h>
12+
13+
#include <zephyr/device.h>
14+
#include <zephyr/devicetree.h>
15+
#include <zephyr/drivers/uart.h>
16+
#include <zephyr/init.h>
17+
#include <zephyr/kernel.h>
18+
19+
#include <zephyr/logging/log.h>
20+
LOG_MODULE_REGISTER(aesc_uart, CONFIG_UART_LOG_LEVEL);
21+
22+
struct uart_aesc_data {
23+
DEVICE_MMIO_NAMED_RAM(regs);
24+
};
25+
26+
struct uart_aesc_config {
27+
DEVICE_MMIO_NAMED_ROM(regs);
28+
uint64_t sys_clk_freq;
29+
uint32_t current_speed;
30+
};
31+
32+
struct uart_aesc_regs {
33+
uint32_t data_width;
34+
uint32_t sampling_sizes;
35+
uint32_t fifo_depths;
36+
uint32_t permissions;
37+
uint32_t read_write;
38+
uint32_t fifo_status;
39+
uint32_t clock_div;
40+
uint32_t frame_cfg;
41+
uint32_t ip;
42+
uint32_t ie;
43+
};
44+
45+
#define DEV_CFG(dev) ((struct uart_aesc_config *)(dev)->config)
46+
#define DEV_DATA(dev) ((struct uart_aesc_data *)(dev)->data)
47+
#define DEV_UART(dev) \
48+
((struct uart_aesc_regs *)DEVICE_MMIO_NAMED_GET(dev, regs))
49+
50+
#define AESC_UART_IRQ_TX_EN BIT(0)
51+
#define AESC_UART_IRQ_RX_EN BIT(1)
52+
#define AESC_UART_FIFO_TX_COUNT_MASK GENMASK(23, 16)
53+
#define AESC_UART_READ_FIFO_VALID_BIT BIT(16)
54+
55+
static void uart_aesc_poll_out(const struct device *dev, unsigned char c)
56+
{
57+
struct uart_aesc_regs *uart = DEV_UART(dev);
58+
59+
while ((uart->fifo_status & AESC_UART_FIFO_TX_COUNT_MASK) == 0) {
60+
/* Wait until transmit fifo is empty */
61+
}
62+
uart->read_write = c;
63+
}
64+
65+
static int uart_aesc_poll_in(const struct device *dev, unsigned char *c)
66+
{
67+
const struct uart_aesc_regs *uart = DEV_UART(dev);
68+
int val;
69+
70+
val = uart->read_write;
71+
if (val & AESC_UART_READ_FIFO_VALID_BIT) {
72+
*c = val & 0xFF;
73+
return 0;
74+
}
75+
76+
return -1;
77+
}
78+
79+
static int uart_aesc_init(const struct device *dev)
80+
{
81+
const struct uart_aesc_config *cfg = DEV_CFG(dev);
82+
volatile uintptr_t *base_addr = (volatile uintptr_t *)DEV_UART(dev);
83+
volatile struct uart_aesc_regs *uart;
84+
85+
DEVICE_MMIO_NAMED_MAP(dev, regs, K_MEM_CACHE_NONE);
86+
LOG_DBG("IP core version: %i.%i.%i.",
87+
ip_id_get_major_version(base_addr),
88+
ip_id_get_minor_version(base_addr),
89+
ip_id_get_patchlevel(base_addr)
90+
);
91+
DEVICE_MMIO_NAMED_GET(dev, regs) = ip_id_relocate_driver(base_addr);
92+
LOG_DBG("Relocate driver to address 0x%lx.", DEVICE_MMIO_NAMED_GET(dev, regs));
93+
uart = DEV_UART(dev);
94+
95+
uart->clock_div = cfg->sys_clk_freq / cfg->current_speed / 8;
96+
uart->frame_cfg = 7;
97+
98+
return 0;
99+
}
100+
101+
static const struct uart_driver_api uart_aesc_driver_api = {
102+
.poll_in = uart_aesc_poll_in,
103+
.poll_out = uart_aesc_poll_out,
104+
.err_check = NULL,
105+
};
106+
107+
#define AESC_UART_INIT(no) \
108+
static struct uart_aesc_data uart_aesc_dev_data_##no; \
109+
static struct uart_aesc_config uart_aesc_dev_cfg_##no = { \
110+
DEVICE_MMIO_NAMED_ROM_INIT(regs, \
111+
DT_INST(no, aesc_uart)), \
112+
.sys_clk_freq = \
113+
DT_PROP(DT_INST(no, aesc_uart), clock_frequency), \
114+
.current_speed = \
115+
DT_PROP(DT_INST(no, aesc_uart), current_speed), \
116+
}; \
117+
DEVICE_DT_INST_DEFINE(no, \
118+
uart_aesc_init, \
119+
NULL, \
120+
&uart_aesc_dev_data_##no, \
121+
&uart_aesc_dev_cfg_##no, \
122+
PRE_KERNEL_1, \
123+
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
124+
(void *)&uart_aesc_driver_api);
125+
126+
DT_INST_FOREACH_STATUS_OKAY(AESC_UART_INIT)

‎dts/bindings/serial/aesc,uart.yaml

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
#
2+
# Copyright (c) 2025 Aesc Silicon
3+
#
4+
# SPDX-License-Identifier: Apache-2.0
5+
#
6+
7+
title: Aesc Silicon UART (Universal Synchronous/Asynchronous Receiver/Transmitter)
8+
9+
description: |
10+
The UART (Universal Asynchronous Receiver-Transmitter) IP Core is a configurable serial
11+
communication interface designed to handle data transmission and reception. The core includes
12+
an internal clock divider and supports flexible frame configurations, allowing for variable data
13+
length, parity, and stop bit settings.
14+
15+
compatible: "aesc,uart"
16+
17+
include: uart-controller.yaml
18+
19+
properties:
20+
reg:
21+
required: true

0 commit comments

Comments
 (0)