dts: bindings: introduce nordic,nrf-pad-groups

Some nordic platforms have quite complex pad groups which
belong to power domains. Introduce bindings for these
groups and describe the pad groups of the nrf54h20.

Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>

Author: bjarki-andreasen

drivers/pinctrl/pinctrl_nrf.c

@@ -111,63 +111,63 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line
 #endif
 
-#define PORT_PD_EXISTS(node_id)									\
+#define PAD_PD_EXISTS(node_id)									\
 	COND_CODE_1(										\
 		DT_NODE_EXISTS(node_id),							\
 		(DT_NODE_HAS_PROP(node_id, power_domains)),					\
 		(0)										\
 	)
 
-#define PORT_PD_DEV_GET_OR_NULL(node_id)							\
+#define PAD_PD_DEV_GET_OR_NULL(node_id)								\
 	COND_CODE_1(										\
 		DT_NODE_EXISTS(node_id),							\
 		(DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, power_domains))),			\
 		(NULL)										\
 	)
 
 #define PORTS_HAVE_PD										\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio0)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio1)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio2)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio3)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio4)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio5)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio6)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio7)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio8)) ||							\
-	PORT_PD_EXISTS(DT_NODELABEL(gpio9))
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p0)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p1)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p2)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p3)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p4)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p5)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p6)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p7)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p8)) ||						\
+	PAD_PD_EXISTS(DT_NODELABEL(pad_group_p9))
 
 #if PORTS_HAVE_PD
 
-static const struct device *const port_pd_devs[] = {
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio0)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio1)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio2)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio3)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio4)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio5)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio6)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio7)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio8)),
-	PORT_PD_DEV_GET_OR_NULL(DT_NODELABEL(gpio9)),
+static const struct device *const pad_pd_devs[] = {
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p0)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p1)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p2)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p3)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p4)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p5)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p6)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p7)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p8)),
+	PAD_PD_DEV_GET_OR_NULL(DT_NODELABEL(pad_group_p9)),
 };
 
-static atomic_t port_pd_masks[ARRAY_SIZE(port_pd_devs)];
+static atomic_t pad_pd_masks[ARRAY_SIZE(pad_pd_devs)];
 
-static int port_pd_request_pin(uint16_t pin_number)
+static int pad_pd_request_pin(uint16_t pin_number)
 {
 	uint8_t port_number = NRF_GET_PORT(pin_number);
 	uint16_t port_pin_number = NRF_GET_PORT_PIN(pin_number);
-	const struct device *port_pd_dev = port_pd_devs[port_number];
-	atomic_t *port_pd_mask = &port_pd_masks[port_number];
+	const struct device *pad_pd_dev = pad_pd_devs[port_number];
+	atomic_t *pad_pd_mask = &pad_pd_masks[port_number];
 
-	if (atomic_test_and_set_bit(port_pd_mask, port_pin_number)) {
+	if (atomic_test_and_set_bit(pad_pd_mask, port_pin_number)) {
 		/* already requested */
 		return 0;
 	}
 
-	if (pm_device_runtime_get(port_pd_dev)) {
-		atomic_clear_bit(port_pd_mask, port_pin_number);
+	if (pm_device_runtime_get(pad_pd_dev)) {
+		atomic_clear_bit(pad_pd_mask, port_pin_number);
 		return -EIO;
 	}
 
@@ -176,24 +176,24 @@ static int port_pd_request_pin(uint16_t pin_number)
 	return 0;
 }
 
-static int port_pd_release_pin(uint16_t pin_number)
+static int pad_pd_release_pin(uint16_t pin_number)
 {
 	uint8_t port_number = NRF_GET_PORT(pin_number);
 	uint16_t port_pin_number = NRF_GET_PORT_PIN(pin_number);
-	const struct device *port_pd_dev = port_pd_devs[port_number];
-	atomic_t *port_pd_mask = &port_pd_masks[port_number];
+	const struct device *pad_pd_dev = pad_pd_devs[port_number];
+	atomic_t *pad_pd_mask = &pad_pd_masks[port_number];
 
-	if (!atomic_test_and_clear_bit(port_pd_mask, port_pin_number)) {
+	if (!atomic_test_and_clear_bit(pad_pd_mask, port_pin_number)) {
 		/* already released */
 		return 0;
 	}
 
 	/* power domain may become inactive, retain shall be enabled */
 	nrf_gpio_pin_retain_enable(pin_number);
 
-	if (pm_device_runtime_put(port_pd_dev)) {
+	if (pm_device_runtime_put(pad_pd_dev)) {
 		nrf_gpio_pin_retain_disable(pin_number);
-		atomic_set_bit(port_pd_mask, port_pin_number);
+		atomic_set_bit(pad_pd_mask, port_pin_number);
 		return -EIO;
 	}
 
@@ -202,13 +202,13 @@ static int port_pd_release_pin(uint16_t pin_number)
 
 #else
 
-static int port_pd_request_pin(uint16_t pin_number)
+static int pad_pd_request_pin(uint16_t pin_number)
 {
 	ARG_UNUSED(pin_number);
 	return 0;
 }
 
-static int port_pd_release_pin(uint16_t pin_number)
+static int pad_pd_release_pin(uint16_t pin_number)
 {
 	ARG_UNUSED(pin_number);
 	return 0;
@@ -590,7 +590,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			uint32_t pin = psel;
 
 			/* enable pin */
-			port_pd_request_pin(pin);
+			pad_pd_request_pin(pin);
 			port_pin_clock_set(pin, NRF_GET_CLOCKPIN_ENABLE(pins[i]));
 
 			if (write != NO_WRITE) {
@@ -609,7 +609,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 
 			if (NRF_GET_LP(pins[i]) == NRF_LP_ENABLE) {
 				/* disable pin */
-				port_pd_release_pin(pin);
+				pad_pd_release_pin(pin);
 				port_pin_clock_set(pin, false);
 			}
 		}

dts/bindings/gpio/nordic,nrf-gpio.yaml

@@ -37,6 +37,12 @@ properties:
 
         port = <1>;
 
+  pad-group:
+    type: phandle
+    description: |
+      The pad group this GPIO port can be muxed to. The pad group is
+      presumed to be "always on" if omitted.
+
 gpio-cells:
   - pin
   - flags

dts/bindings/misc/nordic,nrf-pad-groups.yaml

@@ -0,0 +1,33 @@
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Nordic nRF pad groups.
+
+  The pad groups describe groups of pads connected to
+  package pins of the SoC. A pad group will have a
+  combination of IO, VDD and GND pads. A pad group
+  will have a single supply and belong to a single
+  power domain.
+
+compatible: "nordic,nrf-pad-groups"
+
+child-binding:
+  description: Nordic nRF GPIO pad group.
+
+  properties:
+    power-domains:
+      type: phandle-array
+      description: Pad group's power domain.
+
+    data-pads-mask:
+      type: int
+      description: Mask of data pads.
+
+    clock-pads-mask:
+      type: int
+      description: Mask of clock pads.
+
+    fast-pads-mask:
+      type: int
+      description: Mask of fast pads.

dts/vendor/nordic/nrf54h20.dtsi

@@ -246,6 +246,34 @@
 		status = "disabled";
 	};
 
+	pad-groups {
+		compatible = "nordic,nrf-pad-groups";
+
+		pad_group_p0: p0 {
+			power-domains = <&gdpwr_slow_main>;
+		};
+
+		pad_group_p1: p1 {
+			power-domains = <&gdpwr_slow_main>;
+		};
+
+		pad_group_p2: p2 {
+			power-domains = <&gdpwr_slow_main>;
+		};
+
+		pad_group_p6: p6 {
+			power-domains = <&gdpwr_fast_active_1>;
+		};
+
+		pad_group_p7: p7 {
+			power-domains = <&gdpwr_fast_active_1>;
+		};
+
+		pad_group_p9: p9 {
+			power-domains = <&gdpwr_slow_main>;
+		};
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -848,6 +876,7 @@
 				gpiote-instance = <&gpiote130>;
 				ngpios = <12>;
 				port = <0>;
+				pad-group = <&pad_group_p0>;
 			};
 
 			gpio1: gpio@938200 {
@@ -860,6 +889,7 @@
 				gpiote-instance = <&gpiote130>;
 				ngpios = <12>;
 				port = <1>;
+				pad-group = <&pad_group_p1>;
 			};
 
 			gpio2: gpio@938400 {
@@ -872,6 +902,7 @@
 				gpiote-instance = <&gpiote130>;
 				ngpios = <12>;
 				port = <2>;
+				pad-group = <&pad_group_p2>;
 			};
 
 			gpio6: gpio@938c00 {
@@ -880,11 +911,10 @@
 				status = "disabled";
 				#gpio-cells = <2>;
 				gpio-controller;
-				power-domains = <&gdpwr_slow_main>,
-						<&gdpwr_fast_active_1>;
-				power-domain-names = "peripheral", "pad";
+				power-domains = <&gdpwr_slow_main>;
 				ngpios = <14>;
 				port = <6>;
+				pad-group = <&pad_group_p6>;
 			};
 
 			gpio7: gpio@938e00 {
@@ -893,11 +923,10 @@
 				status = "disabled";
 				#gpio-cells = <2>;
 				gpio-controller;
-				power-domains = <&gdpwr_slow_main>,
-						<&gdpwr_fast_active_1>;
-				power-domain-names = "peripheral", "pad";
+				power-domains = <&gdpwr_slow_main>;
 				ngpios = <8>;
 				port = <7>;
+				pad-group = <&pad_group_p7>;
 			};
 
 			gpio9: gpio@939200 {
@@ -910,6 +939,7 @@
 				gpiote-instance = <&gpiote130>;
 				ngpios = <6>;
 				port = <9>;
+				pad-group = <&pad_group_p9>;
 			};
 
 			dppic131: dppic@981000 {