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boards: nxp: imx943_evk: add NETC switch support for M33
Added NETC switch support for M33. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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3 files changed

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boards/nxp/imx943_evk/doc/index.rst

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@@ -65,10 +65,13 @@ CPU's UART1 for Cortex-A55, and UART8 for Cortex-M33.
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Ethernet
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--------
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NETC driver supports to manage the Physical Station Interface (PSI).
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NETC driver supports to manage the Physical Station Interface (PSI), and TSN switch.
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The ENET0, ENETC1, ENETC2 ports could be enabled for M33 by west build option
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``-DEXTRA_DTC_OVERLAY_FILE=enetc.overlay``.
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The two switch ports could be enabled for M33 by west build option.
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``-DEXTRA_DTC_OVERLAY_FILE=netc-switch.overlay``.
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Programming and Debugging (A55)
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*******************************
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&emdio {
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status = "okay";
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phy0: phy@2 {
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status = "okay";
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};
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phy1: phy@3 {
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status = "okay";
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};
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};
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/* Internal port */
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&enetc_psi3 {
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status = "okay";
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};
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&netc_switch {
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status = "okay";
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switch_port0: switch_port@0 {
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status = "okay";
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};
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switch_port1: switch_port@1 {
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status = "okay";
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};
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/* Internal port */
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switch_port3: switch_port@3 {
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status = "okay";
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};
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};

boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts

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@@ -28,15 +28,15 @@
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pinctrl-names = "default";
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status = "disabled";
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phy0: phy@f {
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phy0: phy@2 {
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compatible = "ethernet-phy";
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reg = <0xf>;
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reg = <0x2>;
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status = "disabled";
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};
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phy1: phy@10 {
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phy1: phy@3 {
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compatible = "ethernet-phy";
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reg = <0x10>;
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reg = <0x3>;
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status = "disabled";
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};
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pinctrl-0 = <&lpuart8_default>;
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pinctrl-names = "default";
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};
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&switch_port0 {
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zephyr,random-mac-address;
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pinctrl-0 = <&eth0_default>;
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pinctrl-names = "default";
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phy-handle = <&phy0>;
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phy-connection-type = "mii";
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status = "disabled";
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};
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&switch_port1 {
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zephyr,random-mac-address;
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pinctrl-0 = <&eth1_default>;
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pinctrl-names = "default";
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phy-handle = <&phy1>;
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phy-connection-type = "mii";
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status = "disabled";
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};
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/* Internal port */
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&switch_port3 {
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zephyr,random-mac-address;
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status = "disabled";
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};

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