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drivers: timer: Xilinx AXI Timer Systick Driver
Internal references: FWRIVERHD-4976/FWRIVERHD-4982 Signed-off-by: Alp Sayin <alpsayin@gmail.com>
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‎drivers/timer/CMakeLists.txt

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@@ -34,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_SAM0_RTC_TIMER sam0_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c)
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zephyr_library_sources_ifdef(CONFIG_TI_DM_TIMER ti_dmtimer.c)
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zephyr_library_sources_ifdef(CONFIG_XLNX_PSTTC_TIMER xlnx_psttc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_XLNX_TMRCTR xlnx_tmrctr.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c)
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zephyr_library_sources_ifdef(CONFIG_MTK_ADSP_TIMER mtk_adsp_timer.c)

‎drivers/timer/Kconfig

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@@ -94,6 +94,7 @@ source "drivers/timer/Kconfig.smartbond"
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source "drivers/timer/Kconfig.stm32_lptim"
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source "drivers/timer/Kconfig.ti_dm_timer"
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source "drivers/timer/Kconfig.xlnx_psttc"
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source "drivers/timer/Kconfig.xlnx_tmrctr"
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source "drivers/timer/Kconfig.xtensa"
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source "drivers/timer/Kconfig.mtk_adsp"
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‎drivers/timer/Kconfig.xlnx_tmrctr

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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config XLNX_TMRCTR
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bool "Xilinx AXI Timer/Counter"
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select TICKLESS_CAPABLE
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default y if MICROBLAZE
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help
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This module implements a kernel device driver for the MICROBLAZE AXI Timer devices.
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AXI timer is not capable of matching against a preloaded value. Thus, it's not
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capable of providing TICKLESS_KERNEL.
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config XLNX_TMRCTR_TIMER_INDEX
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int "Xilinx TMRCTR timer index"
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default 0
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depends on XLNX_TMRCTR
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help
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This is the index of timer/counter picked to provide system clock.

‎drivers/timer/xlnx_tmrctr.c

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/arch/cpu.h>
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#include <soc.h>
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#define DT_DRV_COMPAT xlnx_tmrctr
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#define IRQ_TIMER DT_INST_IRQN(CONFIG_XLNX_TMRCTR_TIMER_INDEX)
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#define TIMER_CYCLES_PER_SEC DT_INST_PROP(CONFIG_XLNX_TMRCTR_TIMER_INDEX, clock_frequency)
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#define BASE_ADDRESS DT_INST_REG_ADDR(0)
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#define TICK_TIMER_COUNTER_NUMBER 0U
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#define SYS_CLOCK_COUNTER_NUMBER 1U
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#define TIMER_CYCLES_PER_TICK (TIMER_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define TICK_TIMER_TOP_VALUE (TIMER_CYCLES_PER_TICK - 1UL)
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#define NUM_COUNTERS 2
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/* Register definitions */
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#define XTC_TCSR_OFFSET 0 /**< Control/Status register */
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#define XTC_TLR_OFFSET 4 /**< Load register */
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#define XTC_TCR_OFFSET 8 /**< Timer counter register */
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/* Control status register mask */
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#define XTC_CSR_CASC_MASK 0x00000800
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#define XTC_CSR_ENABLE_ALL_MASK 0x00000400
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#define XTC_CSR_ENABLE_PWM_MASK 0x00000200
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#define XTC_CSR_INT_OCCURRED_MASK 0x00000100
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#define XTC_CSR_ENABLE_TMR_MASK 0x00000080
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#define XTC_CSR_ENABLE_INT_MASK 0x00000040
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#define XTC_CSR_LOAD_MASK 0x00000020
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#define XTC_CSR_AUTO_RELOAD_MASK 0x00000010
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#define XTC_CSR_EXT_CAPTURE_MASK 0x00000008
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#define XTC_CSR_EXT_GENERATE_MASK 0x00000004
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#define XTC_CSR_DOWN_COUNT_MASK 0x00000002
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#define XTC_CSR_CAPTURE_MODE_MASK 0x00000001
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/* 1st counter is at offset 0, 2nd counter is at offset 16 */
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#define NUM_REGS_PER_COUNTER 16
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#define COUNTER_REG_OFFSET(idx) (NUM_REGS_PER_COUNTER * idx)
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/*
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* CYCLES_NEXT_MIN must be large enough to ensure that the timer does not miss
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* interrupts. This value was conservatively set, and there is room for improvement.
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*/
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#define CYCLES_NEXT_MIN (TIMER_CYCLES_PER_SEC / 5000)
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/* We allow only half the maximum numerical range of the cycle counters so that we
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* can never miss a sysclock overflow. This is also being very conservative.
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*/
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#define CYCLES_NEXT_MAX (0xFFFFFFFFU / 2)
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static volatile uint32_t last_cycles;
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BUILD_ASSERT(TIMER_CYCLES_PER_SEC >= CONFIG_SYS_CLOCK_TICKS_PER_SEC,
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"Timer clock frequency must be greater than the system tick "
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"frequency");
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BUILD_ASSERT((TIMER_CYCLES_PER_SEC % CONFIG_SYS_CLOCK_TICKS_PER_SEC) == 0,
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"Timer clock frequency is not divisible by the system tick "
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"frequency");
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC % TIMER_CYCLES_PER_SEC) == 0,
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"CPU clock frequency is not divisible by the Timer clock frequency "
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"frequency");
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enum xlnx_tmrctr_state {
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XLNX_TMRCTR_INIT, /* Initial (inactive) state */
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XLNX_TMRCTR_READY, /* Initialised */
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XLNX_TMRCTR_RUNNING /* Started */
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};
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struct xlnx_tmrctr_data {
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mm_reg_t base;
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enum xlnx_tmrctr_state state;
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};
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struct xlnx_tmrctr_data xlnx_tmrctr = {
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.base = BASE_ADDRESS,
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.state = XLNX_TMRCTR_INIT,
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};
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#define xlnx_tmrctr_read32(counter_number, offset) \
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sys_read32(BASE_ADDRESS + COUNTER_REG_OFFSET(counter_number) + offset)
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#define xlnx_tmrctr_write32(counter_number, value, offset) \
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sys_write32(value, BASE_ADDRESS + COUNTER_REG_OFFSET(counter_number) + offset)
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volatile uint32_t xlnx_tmrctr_read_count(void)
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{
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return xlnx_tmrctr_read32(SYS_CLOCK_COUNTER_NUMBER, XTC_TCR_OFFSET);
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}
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volatile uint32_t xlnx_tmrctr_read_hw_cycle_count(void)
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{
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return (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / TIMER_CYCLES_PER_SEC) *
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xlnx_tmrctr_read_count();
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}
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static void xlnx_tmrctr_clear_interrupt(void)
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{
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uint32_t control_status_register =
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xlnx_tmrctr_read32(TICK_TIMER_COUNTER_NUMBER, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(TICK_TIMER_COUNTER_NUMBER,
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control_status_register | XTC_CSR_INT_OCCURRED_MASK, XTC_TCSR_OFFSET);
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}
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static inline void xlnx_tmrctr_set_reset_value(uint8_t counter_number, uint32_t reset_value)
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{
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xlnx_tmrctr_write32(counter_number, reset_value, XTC_TLR_OFFSET);
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}
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static inline void xlnx_tmrctr_set_options(uint8_t counter_number, uint32_t options)
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{
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xlnx_tmrctr_write32(counter_number, options, XTC_TCSR_OFFSET);
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}
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#ifdef CONFIG_TICKLESS_KERNEL
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static void xlnx_tmrctr_reload_tick_timer(uint32_t delta_cycles)
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{
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uint32_t csr_val;
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uint32_t cur_cycle_count = xlnx_tmrctr_read_count();
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/* Ensure that the delta_cycles value meets the timing requirements */
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if (delta_cycles < CYCLES_NEXT_MIN) {
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/* Don't risk missing an interrupt */
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delta_cycles = CYCLES_NEXT_MIN;
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}
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if (delta_cycles > CYCLES_NEXT_MAX - cur_cycle_count) {
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/* Don't risk missing a sysclock overflow */
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delta_cycles = CYCLES_NEXT_MAX - cur_cycle_count;
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}
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/* Write counter load value for interrupt generation */
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xlnx_tmrctr_set_reset_value(TICK_TIMER_COUNTER_NUMBER, delta_cycles);
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/* Load the load value */
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csr_val = xlnx_tmrctr_read32(TICK_TIMER_COUNTER_NUMBER, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(TICK_TIMER_COUNTER_NUMBER, csr_val | XTC_CSR_LOAD_MASK,
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XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(TICK_TIMER_COUNTER_NUMBER, csr_val, XTC_TCSR_OFFSET);
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}
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#endif /* CONFIG_TICKLESS_KERNEL */
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static void xlnx_tmrctr_irq_handler(const void *unused)
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{
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uint32_t cycles;
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uint32_t delta_ticks;
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ARG_UNUSED(unused);
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cycles = xlnx_tmrctr_read_count();
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/* Calculate the number of ticks since last announcement */
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delta_ticks = (cycles - last_cycles) / TIMER_CYCLES_PER_TICK;
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/* Update last cycles count without the rounding error */
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last_cycles += (delta_ticks * TIMER_CYCLES_PER_TICK);
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/* Announce to the kernel*/
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sys_clock_announce(delta_ticks);
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xlnx_tmrctr_clear_interrupt();
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xlnx_intc_irq_acknowledge(BIT(IRQ_TIMER));
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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uint32_t cycles;
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uint32_t delta_cycles;
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/* Read counter value */
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cycles = xlnx_tmrctr_read_count();
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/* Calculate timeout counter value */
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if (ticks == K_TICKS_FOREVER) {
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delta_cycles = CYCLES_NEXT_MAX;
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} else {
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delta_cycles = ((uint32_t)ticks * TIMER_CYCLES_PER_TICK);
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}
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/* Set timer reload value for the next interrupt */
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xlnx_tmrctr_reload_tick_timer(delta_cycles);
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#endif
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}
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uint32_t sys_clock_elapsed(void)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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uint32_t cycles = xlnx_tmrctr_read_count();
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return (cycles - last_cycles) / TIMER_CYCLES_PER_TICK;
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#else
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/* Always return 0 for tickful operation */
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return 0;
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#endif
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return xlnx_tmrctr_read_hw_cycle_count();
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}
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static int xlnx_tmrctr_initialize(void)
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{
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if (xlnx_tmrctr.state != XLNX_TMRCTR_INIT) {
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return -EEXIST;
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}
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xlnx_tmrctr.state = XLNX_TMRCTR_READY;
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for (uint8_t counter_number = 0; counter_number < NUM_COUNTERS; counter_number++) {
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/* Set the compare register to 0. */
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xlnx_tmrctr_write32(counter_number, 0, XTC_TLR_OFFSET);
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/* Reset the timer and the interrupt. */
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xlnx_tmrctr_write32(counter_number, XTC_CSR_INT_OCCURRED_MASK | XTC_CSR_LOAD_MASK,
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XTC_TCSR_OFFSET);
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/* Release the reset. */
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xlnx_tmrctr_write32(counter_number, 0, XTC_TCSR_OFFSET);
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}
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return 0;
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}
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static int xlnx_tmrctr_start(void)
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{
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if (xlnx_tmrctr.state == XLNX_TMRCTR_INIT) {
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return -ENODEV;
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}
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if (xlnx_tmrctr.state == XLNX_TMRCTR_RUNNING) {
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return -EALREADY;
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}
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int control_status_register = xlnx_tmrctr_read32(
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TICK_TIMER_COUNTER_NUMBER, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(TICK_TIMER_COUNTER_NUMBER, XTC_CSR_LOAD_MASK, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(TICK_TIMER_COUNTER_NUMBER,
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control_status_register | XTC_CSR_ENABLE_TMR_MASK, XTC_TCSR_OFFSET);
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control_status_register = xlnx_tmrctr_read32(SYS_CLOCK_COUNTER_NUMBER, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(SYS_CLOCK_COUNTER_NUMBER, XTC_CSR_LOAD_MASK, XTC_TCSR_OFFSET);
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xlnx_tmrctr_write32(SYS_CLOCK_COUNTER_NUMBER,
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control_status_register | XTC_CSR_ENABLE_TMR_MASK, XTC_TCSR_OFFSET);
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xlnx_tmrctr.state = XLNX_TMRCTR_RUNNING;
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return 0;
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}
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static int sys_clock_driver_init(void)
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{
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int status = xlnx_tmrctr_initialize();
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if (status != 0) {
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return status;
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}
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#if !defined(CONFIG_TICKLESS_KERNEL)
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xlnx_tmrctr_set_reset_value(TICK_TIMER_COUNTER_NUMBER, CYCLES_NEXT_MAX);
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xlnx_tmrctr_set_options(TICK_TIMER_COUNTER_NUMBER, XTC_CSR_ENABLE_INT_MASK |
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XTC_CSR_DOWN_COUNT_MASK);
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#else
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xlnx_tmrctr_set_reset_value(TICK_TIMER_COUNTER_NUMBER, TIMER_CYCLES_PER_TICK);
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xlnx_tmrctr_set_options(TICK_TIMER_COUNTER_NUMBER, XTC_CSR_ENABLE_INT_MASK |
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XTC_CSR_AUTO_RELOAD_MASK |
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XTC_CSR_DOWN_COUNT_MASK);
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#endif
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xlnx_tmrctr_set_options(SYS_CLOCK_COUNTER_NUMBER, XTC_CSR_AUTO_RELOAD_MASK);
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status = xlnx_tmrctr_start();
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if (status != 0) {
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return status;
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}
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last_cycles = xlnx_tmrctr_read_count();
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IRQ_CONNECT(IRQ_TIMER, 0, xlnx_tmrctr_irq_handler, NULL, 0);
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irq_enable(IRQ_TIMER);
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return 0;
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}
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#if defined(CONFIG_MICROBLAZE)
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/**
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* @brief Overwrite cycle based busy wait
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* Implementation is derived from z_impl_k_busy_wait@kernel/timeout.c
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*
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* @param usec_to_wait
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* @note Microblaze arch already implements an unaccurate, nop based
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* no-timer-required busy wait. This routine simply overrides it with
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* a much more accurate version.
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*/
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void arch_busy_wait(uint32_t usec_to_wait)
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{
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uint32_t start_cycles = xlnx_tmrctr_read_count();
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/* use 64-bit math to prevent overflow when multiplying */
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uint32_t cycles_to_wait =
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(uint32_t)((uint64_t)usec_to_wait * (uint64_t)TIMER_CYCLES_PER_SEC /
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(uint64_t)USEC_PER_SEC);
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for (;;) {
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uint32_t current_cycles = xlnx_tmrctr_read_count();
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/* this handles the rollover on an unsigned 32-bit value */
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if ((current_cycles - start_cycles) >= cycles_to_wait) {
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break;
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}
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}
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}
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#endif
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);

‎dts/bindings/timer/xlnx,tmrctr.yaml

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# Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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# Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Xilinx AXI TMRCTR timer counter
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compatible: "xlnx,tmrctr"
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include: base.yaml
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properties:
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reg:
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required: true
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clock-frequency:
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type: int
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required: true
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description: Clock frequency information for Timer operation

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