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drivers: audio: intel: add support for microphone privacy
Implements driver for Intel microphone privacy feature. Signed-off-by: Michal Bukowski <michal.bukowski@intel.com>
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‎drivers/CMakeLists.txt

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@@ -53,6 +53,7 @@ add_subdirectory_ifdef(CONFIG_I2S i2s)
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add_subdirectory_ifdef(CONFIG_I3C i3c)
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add_subdirectory_ifdef(CONFIG_IEEE802154 ieee802154)
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add_subdirectory_ifdef(CONFIG_INPUT input)
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add_subdirectory_ifdef(CONFIG_INTEL_ADSP_MIC_PRIVACY audio/mic_privacy/intel)
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add_subdirectory_ifdef(CONFIG_IPM ipm)
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add_subdirectory_ifdef(CONFIG_KSCAN kscan)
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add_subdirectory_ifdef(CONFIG_LED led)

‎drivers/Kconfig

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@@ -8,6 +8,7 @@ menu "Device Drivers"
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# zephyr-keep-sorted-start
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source "drivers/adc/Kconfig"
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source "drivers/audio/Kconfig"
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source "drivers/audio/mic_privacy/intel/Kconfig.mic_privacy"
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source "drivers/auxdisplay/Kconfig"
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source "drivers/bbram/Kconfig"
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source "drivers/bluetooth/Kconfig"

‎drivers/audio/mic_privacy/intel/CMakeLists.txt

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_MIC_PRIVACY mic_privacy.c)

‎drivers/audio/mic_privacy/intel/Kconfig.mic_privacy

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# SOF Microphone Privacy configuration options
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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config INTEL_ADSP_MIC_PRIVACY
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bool "MIC PRIVACY device driver support"
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default y
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depends on DT_HAS_INTEL_ADSP_MIC_PRIVACY_ENABLED
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help
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Enable MIC PRIVACY device driver

‎drivers/audio/mic_privacy/intel/mic_privacy.c

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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include "mic_privacy_registers.h"
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#include <zephyr/drivers/mic_privacy/intel/mic_privacy.h>
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#include <zephyr/irq.h>
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#include <zephyr/device.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/pm/device.h>
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#define LOG_DOMAIN mic_priv_zephyr
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#define DT_DRV_COMPAT intel_adsp_mic_privacy
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#define DMICPVC_ADDRESS (DT_INST_REG_ADDR(0))
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#define DFMICPVCP_ADDRESS (DMICPVC_ADDRESS)
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#define DFMICPVCS_ADDRESS (DMICPVC_ADDRESS + 0x0004)
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#define DFFWMICPVCCS_ADDRESS (DMICPVC_ADDRESS + 0x0006)
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#define DMICVSSX_ADDRESS (0x16000)
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#define DMICXLVSCTL_ADDRESS (DMICVSSX_ADDRESS + 0x0004)
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#define DMICXPVCCS_ADDRESS (DMICVSSX_ADDRESS + 0x0010)
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static inline void ace_mic_priv_intc_unmask(void)
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{
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ACE_DINT[0].ie[ACE_INTL_MIC_PRIV] = BIT(0);
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}
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static inline void ace_dmic_intc_unmask(void)
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{
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ACE_DINT[0].ie[ACE_INTL_DMIC] = BIT(0);
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}
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static void mic_privacy_enable_fw_managed_irq(bool enable_irq, const void *fn)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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if (enable_irq) {
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pv_ccs.part.mdstschgie = 1;
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} else {
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pv_ccs.part.mdstschgie = 0;
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}
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sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
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if (enable_irq && !irq_is_enabled(DT_INST_IRQN(0))) {
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irq_connect_dynamic(DT_INST_IRQN(0), 0,
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fn,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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ace_mic_priv_intc_unmask();
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}
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}
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static void mic_privacy_clear_fw_managed_irq(void)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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pv_ccs.part.mdstschg = 1;
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sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
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}
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static void mic_privacy_enable_dmic_irq(bool enable_irq, const void *fn)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
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if (enable_irq) {
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pv_ccs.part.mdstschgie = 1;
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} else {
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pv_ccs.part.mdstschgie = 0;
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}
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sys_write16(pv_ccs.full, DMICXPVCCS_ADDRESS);
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if (enable_irq) {
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irq_connect_dynamic(ACE_INTL_DMIC, 0,
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fn,
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NULL, 0);
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irq_enable(ACE_INTL_DMIC);
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ace_dmic_intc_unmask();
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}
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}
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static bool mic_privacy_get_dmic_irq_status(void)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
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return pv_ccs.part.mdstschg;
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}
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static void mic_privacy_clear_dmic_irq_status(void)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
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pv_ccs.part.mdstschg = 1;
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sys_write16(pv_ccs.full, DMICXPVCCS_ADDRESS);
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}
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static enum mic_privacy_policy mic_privacy_get_policy(void)
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{
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union DFMICPVCP micpvcp;
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micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
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if (micpvcp.part.ddze == 2 && micpvcp.part.ddzpl == 1) {
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return MIC_PRIVACY_HW_MANAGED;
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} else if (micpvcp.part.ddze == 2 && micpvcp.part.ddzpl == 0) {
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return MIC_PRIVACY_FW_MANAGED;
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} else if (micpvcp.part.ddze == 3) {
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return MIC_PRIVACY_FORCE_MIC_DISABLED;
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} else {
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return MIC_PRIVACY_DISABLED;
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}
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}
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static uint32_t mic_privacy_get_privacy_policy_register_raw_value(void)
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{
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return sys_read32(DFMICPVCP_ADDRESS);
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}
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static uint32_t mic_privacy_get_dma_data_zeroing_wait_time(void)
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{
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union DFMICPVCP micpvcp;
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micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
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return micpvcp.part.ddzwt;
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}
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static uint32_t mic_privacy_get_dma_data_zeroing_link_select(void)
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{
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union DFMICPVCP micpvcp;
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micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
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return micpvcp.part.ddzls;
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}
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static uint32_t mic_privacy_get_dmic_mic_disable_status(void)
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{
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union DMICXPVCCS pvccs;
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pvccs.full = sys_read32(DMICXPVCCS_ADDRESS);
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return pvccs.part.mdsts;
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}
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static uint32_t mic_privacy_get_fw_managed_mic_disable_status(void)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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return pv_ccs.part.mdsts;
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}
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static void mic_privacy_set_fw_managed_mode(bool is_fw_managed_enabled)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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if (is_fw_managed_enabled) {
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pv_ccs.part.fmmd = 1;
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} else {
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pv_ccs.part.fmmd = 0;
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}
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sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
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}
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static void mic_privacy_set_fw_mic_disable_status(bool fw_mic_disable_status)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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if (fw_mic_disable_status) {
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pv_ccs.part.fmdsts = 1;
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} else {
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pv_ccs.part.fmdsts = 0;
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}
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sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
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}
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static uint32_t mic_privacy_get_fw_mic_disable_status(void)
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{
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union DFFWMICPVCCS pv_ccs;
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pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
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return pv_ccs.part.fmdsts;
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}
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static int intel_adsp_mic_priv_init(const struct device *dev)
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{
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return 0;
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};
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static const struct mic_privacy_api_funcs mic_privacy_ops = {
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.enable_fw_managed_irq = mic_privacy_enable_fw_managed_irq,
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.clear_fw_managed_irq = mic_privacy_clear_fw_managed_irq,
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.enable_dmic_irq = mic_privacy_enable_dmic_irq,
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.get_dmic_irq_status = mic_privacy_get_dmic_irq_status,
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.clear_dmic_irq_status = mic_privacy_clear_dmic_irq_status,
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.get_policy = mic_privacy_get_policy,
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.get_privacy_policy_register_raw_value = mic_privacy_get_privacy_policy_register_raw_value,
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.get_dma_data_zeroing_wait_time = mic_privacy_get_dma_data_zeroing_wait_time,
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.get_dma_data_zeroing_link_select = mic_privacy_get_dma_data_zeroing_link_select,
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.get_dmic_mic_disable_status = mic_privacy_get_dmic_mic_disable_status,
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.get_fw_managed_mic_disable_status = mic_privacy_get_fw_managed_mic_disable_status,
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.set_fw_managed_mode = mic_privacy_set_fw_managed_mode,
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.set_fw_mic_disable_status = mic_privacy_set_fw_mic_disable_status,
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.get_fw_mic_disable_status = mic_privacy_get_fw_mic_disable_status
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};
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#define INTEL_ADSP_MIC_PRIVACY_INIT(inst) \
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\
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static const struct intel_adsp_mic_priv_cfg intel_adsp_mic_priv##inst##_config = { \
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.base = DT_INST_REG_ADDR(inst), \
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.regblock_size = DT_INST_REG_SIZE(inst), \
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}; \
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\
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static struct intel_adsp_mic_priv_data intel_adsp_mic_priv##inst##_data = {}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &intel_adsp_mic_priv_init, \
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NULL, \
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&intel_adsp_mic_priv##inst##_data, \
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&intel_adsp_mic_priv##inst##_config, POST_KERNEL, \
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0, \
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&mic_privacy_ops); \
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\
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DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_MIC_PRIVACY_INIT)

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