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VijayakannanVijayakannan
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drivers: ethernet: phy: Add Intel IGC PHY driver
Intel IGC(aka Foxville) is a fully integrated MAC and PHY. This commit adds support for the Intel IGC PHY driver with the following features: - Support 10/100/1000 BASE-T. - Auto Negotiation for 10/100/1000 Mbps speeds. - Integration with the MDIO interface for PHY register access. - PHY link interrupt service handler. - Device tree support for PHY configuration and initialization. It uses the MDIO interface to communicate with the PHY and supports modular configuration via the device tree. Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Ling Pei Lee <pei.lee.ling@intel.com>
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‎drivers/ethernet/phy/CMakeLists.txt

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@@ -5,6 +5,7 @@ zephyr_library_sources_ifdef(CONFIG_PHY_GENERIC_MII phy_mii.c)
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# zephyr-keep-sorted-start
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zephyr_library_sources_ifdef(CONFIG_PHY_ADIN2111 phy_adin2111.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_DM8806 phy_dm8806.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_INTEL_IGC phy_intel_igc.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_KSZ8081 phy_microchip_ksz8081.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_T1S phy_microchip_t1s.c)
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zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_VSC8541 phy_microchip_vsc8541.c)

‎drivers/ethernet/phy/Kconfig

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@@ -123,4 +123,12 @@ config PHY_VERIFY_DEVICE_IDENTIFICATION
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Verify the organizationally unique identifier that is reported
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by the phy chip.
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config PHY_INTEL_IGC
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bool "Intel IGC PHY driver"
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default y
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depends on DT_HAS_INTEL_IGC_PHY_ENABLED
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depends on MDIO_INTEL_IGC
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help
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Enable Intel IGC PHY driver.
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endif # "Ethernet PHY Drivers"

‎drivers/ethernet/phy/phy_intel_igc.c

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/*
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* Copyright (c) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/net/phy.h>
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#include <zephyr/net/mii.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/ethernet/eth_intel_plat.h>
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#define DT_DRV_COMPAT intel_igc_phy
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(intel_igc_phy, CONFIG_PHY_LOG_LEVEL);
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#include "phy_mii.h"
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#define PHY_REV_MASK GENMASK(31, 4)
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#define MII_INVALID_PHY_ID UINT32_MAX
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#define PHY_ID_SHIFT 16
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#define PHY_IGC_READ_DELAY 100
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struct phy_intel_igc_cfg {
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const struct device *mdio;
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enum phy_link_speed default_speeds;
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uint8_t phy_addr;
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};
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struct phy_intel_igc_data {
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const struct device *phy;
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struct phy_link_state state;
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struct k_work_delayable link_work;
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phy_callback_t cb;
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void *cb_data;
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};
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static int phy_intel_igc_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, (uint16_t *)value);
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}
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static int phy_intel_igc_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, (uint16_t)value);
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}
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static int phy_intel_igc_id_read(const struct device *dev)
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{
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uint32_t phy_id, value = 0;
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int ret;
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ret = phy_intel_igc_read(dev, MII_PHYID1R, &value);
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if (ret < 0) {
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return ret;
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}
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phy_id = value << PHY_ID_SHIFT;
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ret = phy_intel_igc_read(dev, MII_PHYID2R, &value);
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if (ret < 0) {
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return ret;
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}
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phy_id |= (value & PHY_REV_MASK);
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if (phy_id == MII_INVALID_PHY_ID) {
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return -EINVAL;
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}
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LOG_INF("PHY ID = 0x%x", phy_id);
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return 0;
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}
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static int phy_intel_igc_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds,
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enum phy_cfg_link_flag flags)
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{
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if ((flags & PHY_FLAG_AUTO_NEGOTIATION_DISABLED) != 0) {
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LOG_ERR("Disabling auto-negotiation is not supported by this driver");
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return -ENOTSUP;
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}
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return phy_mii_cfg_link_autoneg(dev, adv_speeds, true);
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}
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static int phy_intel_igc_get_link_state(const struct device *dev, struct phy_link_state *state)
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{
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uint32_t anlpar_val = 0;
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uint32_t anar_val = 0;
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uint32_t c1kt_val = 0;
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uint32_t s1kt_val = 0;
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uint32_t bmsr_val = 0;
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int ret;
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ret = phy_intel_igc_read(dev, MII_BMSR, &bmsr_val);
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if (ret < 0) {
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return ret;
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}
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if ((bmsr_val & MII_BMSR_LINK_STATUS) == 0U) {
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state->is_up = false;
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return 0;
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}
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state->is_up = true;
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ret = phy_intel_igc_read(dev, MII_ANAR, &anar_val);
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if (ret < 0) {
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return ret;
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}
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ret = phy_intel_igc_read(dev, MII_ANLPAR, &anlpar_val);
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if (ret < 0) {
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return ret;
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}
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ret = phy_intel_igc_read(dev, MII_1KTCR, &c1kt_val);
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if (ret < 0) {
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return ret;
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}
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ret = phy_intel_igc_read(dev, MII_1KSTSR, &s1kt_val);
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if (ret < 0) {
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return ret;
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}
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s1kt_val = (s1kt_val >> 2) & 0xFFFF;
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if ((c1kt_val & s1kt_val & MII_ADVERTISE_1000_FULL) != 0U) {
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state->speed = LINK_FULL_1000BASE;
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} else if ((anar_val & anlpar_val & MII_ADVERTISE_100_FULL) != 0U) {
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state->speed = LINK_FULL_100BASE;
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} else if ((anar_val & anlpar_val & MII_ADVERTISE_100_HALF) != 0U) {
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state->speed = LINK_HALF_100BASE;
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} else if ((anar_val & anlpar_val & MII_ADVERTISE_10_FULL) != 0U) {
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state->speed = LINK_FULL_10BASE;
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} else {
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state->speed = LINK_HALF_10BASE;
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}
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return 0;
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}
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static void invoke_link_cb(const struct device *dev)
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{
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struct phy_intel_igc_data *const data = dev->data;
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if (data->cb == NULL) {
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return;
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}
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data->cb(data->phy, &data->state, data->cb_data);
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}
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static int phy_intel_igc_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
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{
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struct phy_intel_igc_data *data = dev->data;
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data->cb = cb;
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data->cb_data = user_data;
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invoke_link_cb(dev);
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return 0;
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}
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static void update_link_state(struct k_work *work)
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{
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struct k_work_delayable *dwork = k_work_delayable_from_work(work);
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struct phy_intel_igc_data *data = CONTAINER_OF(dwork, struct phy_intel_igc_data, link_work);
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const struct device *dev = data->phy;
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struct phy_link_state new_state = {0};
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if (phy_intel_igc_get_link_state(dev, &new_state) < 0) {
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LOG_DBG("Failed to read PHY status registers");
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}
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if (new_state.is_up != data->state.is_up || new_state.speed != data->state.speed) {
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data->state.is_up = new_state.is_up;
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data->state.speed = new_state.speed;
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invoke_link_cb(dev);
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if (data->state.is_up) {
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LOG_INF("PHY Link is Up with Speed %s Mbps & %s duplex",
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PHY_LINK_IS_SPEED_1000M(new_state.speed)
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? "1000"
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: (PHY_LINK_IS_SPEED_100M(new_state.speed) ? "100" : "10"),
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PHY_LINK_IS_FULL_DUPLEX(new_state.speed) ? "Full" : "Half");
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} else {
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LOG_INF("PHY Link is Down");
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}
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}
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}
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void eth_intel_igc_misc_phy_link_isr(const struct device *dev)
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{
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struct phy_intel_igc_data *data = dev->data;
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k_work_reschedule(&data->link_work, K_NO_WAIT);
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}
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static int phy_intel_igc_init(const struct device *dev)
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{
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const struct phy_intel_igc_cfg *const cfg = dev->config;
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int ret;
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ret = phy_intel_igc_id_read(dev);
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if (ret < 0) {
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LOG_ERR("Failed to read PHY ID");
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return ret;
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}
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return phy_intel_igc_cfg_link(dev, cfg->default_speeds, 0);
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}
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static DEVICE_API(ethphy, phy_api) = {
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.get_link = phy_intel_igc_get_link_state,
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.cfg_link = phy_intel_igc_cfg_link,
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.link_cb_set = phy_intel_igc_link_cb_set,
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.read = phy_intel_igc_read,
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.write = phy_intel_igc_write,
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};
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#define IGC_PHY_GENERATE_DEFAULT_SPEEDS(n) \
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((DT_INST_ENUM_HAS_VALUE(n, default_speeds, 10base_half_duplex) ? LINK_HALF_10BASE : 0) | \
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(DT_INST_ENUM_HAS_VALUE(n, default_speeds, 10base_full_duplex) ? LINK_FULL_10BASE : 0) | \
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(DT_INST_ENUM_HAS_VALUE(n, default_speeds, 100base_half_duplex) ? LINK_HALF_100BASE \
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: 0) | \
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(DT_INST_ENUM_HAS_VALUE(n, default_speeds, 100base_full_duplex) ? LINK_FULL_100BASE \
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: 0) | \
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(DT_INST_ENUM_HAS_VALUE(n, default_speeds, 1000base_full_duplex) ? LINK_FULL_1000BASE \
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: 0))
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#define INTEL_IGC_PHY_CONFIG(n) \
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BUILD_ASSERT(IGC_PHY_GENERATE_DEFAULT_SPEEDS(n) != 0, \
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"At least one valid speed must be configured for this driver"); \
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static const struct phy_intel_igc_cfg phy_cfg_##n = { \
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.mdio = DEVICE_DT_GET(DT_INST_PARENT(n)), \
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.phy_addr = DT_INST_REG_ADDR(n), \
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.default_speeds = IGC_PHY_GENERATE_DEFAULT_SPEEDS(n)};
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#define INTEL_IGC_PHY_INIT(n) \
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INTEL_IGC_PHY_CONFIG(n); \
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static struct phy_intel_igc_data phy_data_##n = { \
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.link_work = Z_WORK_DELAYABLE_INITIALIZER(update_link_state), \
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.phy = DEVICE_DT_INST_GET(n), \
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}; \
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DEVICE_DT_INST_DEFINE(n, &phy_intel_igc_init, NULL, &phy_data_##n, &phy_cfg_##n, \
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POST_KERNEL, CONFIG_PHY_INIT_PRIORITY, &phy_api);
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DT_INST_FOREACH_STATUS_OKAY(INTEL_IGC_PHY_INIT)

‎dts/bindings/ethernet/phy/intel,igc-phy.yaml

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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: Intel IGC PHY documentation.
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compatible: "intel,igc-phy"
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include: [ethernet-phy.yaml]
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properties:
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reg:
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required: true
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description: PHY address.

‎include/zephyr/drivers/ethernet/eth_intel_plat.h

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*/
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extern uint32_t eth_intel_get_pcie_bdf(const struct device *dev);
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/**
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* @brief This ISR will be called if there is any link change in the PHY.
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* This interrupt is part of the Miscellaneous interrupt vector.
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*
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* @param dev Pointer to the device structure.
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*/
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extern void eth_intel_igc_misc_phy_link_isr(const struct device *dev);
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#endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_INTEL_PLAT_H__ */

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