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drivers: video: Add PxP m2m driver
The NXP's PxP is a 2D pixel engine which is capable to do some image transformation such as rotation, flipping, color conversion, etc. Make a driver for it in the video m2m category. Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
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8 files changed

+365
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lines changed

‎drivers/video/CMakeLists.txt

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@@ -8,6 +8,7 @@ zephyr_library_sources(video_device.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_CSI video_mcux_csi.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_MIPI_CSI2RX video_mcux_mipi_csi2rx.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_PXP video_mcux_pxp.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_SHELL video_shell.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_SW_GENERATOR video_sw_generator.c)
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zephyr_library_sources_ifdef(CONFIG_VIDEO_MT9M114 mt9m114.c)

‎drivers/video/Kconfig

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@@ -64,6 +64,8 @@ source "drivers/video/Kconfig.mcux_csi"
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source "drivers/video/Kconfig.mcux_mipi_csi2rx"
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source "drivers/video/Kconfig.mcux_pxp"
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source "drivers/video/Kconfig.shell"
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source "drivers/video/Kconfig.sw_generator"

‎drivers/video/Kconfig.mcux_pxp

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# NXP PxP driver configuration option
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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config VIDEO_MCUX_PXP
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bool "NXP MCUX PxP driver"
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default y
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depends on DT_HAS_NXP_PXP_ENABLED

‎drivers/video/video_mcux_pxp.c

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <zephyr/drivers/video.h>
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#include <zephyr/drivers/video-controls.h>
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#include <zephyr/dt-bindings/video/video-interfaces.h>
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#include <zephyr/irq.h>
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#include <zephyr/kernel.h>
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#include <zephyr/logging/log.h>
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#include "video_ctrls.h"
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#include "video_device.h"
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#include <fsl_pxp.h>
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#ifdef CONFIG_HAS_MCUX_CACHE
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#include <fsl_cache.h>
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#endif
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#define DT_DRV_COMPAT nxp_pxp
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LOG_MODULE_REGISTER(mcux_pxp, CONFIG_VIDEO_LOG_LEVEL);
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struct mcux_pxp_config {
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PXP_Type *base;
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void (*irq_config_func)(void);
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};
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struct mcux_pxp_ctrls {
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struct {
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struct video_ctrl rotation;
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struct video_ctrl hflip;
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struct video_ctrl vflip;
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};
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};
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struct mcux_pxp_data {
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struct mcux_pxp_ctrls ctrls;
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pxp_ps_buffer_config_t ps_buffer_cfg;
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pxp_output_buffer_config_t output_buffer_cfg;
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struct k_fifo fifo_in_queued;
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struct k_fifo fifo_in_done;
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struct k_fifo fifo_out_queued;
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struct k_fifo fifo_out_done;
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};
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static void mcux_pxp_isr(const struct device *const dev)
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{
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const struct mcux_pxp_config *config = dev->config;
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struct mcux_pxp_data *data = dev->data;
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PXP_ClearStatusFlags(config->base, kPXP_CompleteFlag);
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struct video_buffer *vbuf_in = k_fifo_get(&data->fifo_in_queued, K_NO_WAIT);
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struct video_buffer *vbuf_out = k_fifo_get(&data->fifo_out_queued, K_NO_WAIT);
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/* Something went wrong, should never happen */
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if ((uint32_t)vbuf_in->buffer != data->ps_buffer_cfg.bufferAddr ||
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(uint32_t)vbuf_out->buffer != data->output_buffer_cfg.buffer0Addr) {
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return;
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}
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vbuf_out->timestamp = k_uptime_get_32();
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vbuf_out->bytesused = data->output_buffer_cfg.pitchBytes * data->output_buffer_cfg.height;
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_InvalidateByRange((uint32_t)vbuf_out->buffer, vbuf_out->bytesused);
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#endif
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k_fifo_put(&data->fifo_in_done, vbuf_in);
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k_fifo_put(&data->fifo_out_done, vbuf_out);
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}
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static int mcux_pxp_get_caps(const struct device *dev, struct video_caps *caps)
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{
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/* TODO */
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return 0;
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}
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static int mcux_pxp_get_fmt(const struct device *dev, struct video_format *fmt)
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{
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/* TODO */
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return 0;
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}
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static int mcux_pxp_set_fmt(const struct device *dev, struct video_format *fmt)
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{
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struct mcux_pxp_data *data = dev->data;
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fmt->pitch = fmt->width * video_bits_per_pixel(fmt->pixelformat) / BITS_PER_BYTE;
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switch (fmt->type) {
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case VIDEO_BUF_TYPE_INPUT:
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data->ps_buffer_cfg.pitchBytes = fmt->pitch;
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switch (fmt->pixelformat) {
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case VIDEO_PIX_FMT_RGB565:
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data->ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatRGB565;
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break;
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case VIDEO_PIX_FMT_RGB24:
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#if (!(defined(FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT) && \
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FSL_FEATURE_PXP_HAS_NO_EXTEND_PIXEL_FORMAT)) && \
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(!(defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3))
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data->ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888;
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#else
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data->ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatRGB888;
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#endif
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break;
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case VIDEO_PIX_FMT_ARGB32:
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case VIDEO_PIX_FMT_XRGB32:
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data->ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888;
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break;
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default:
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return -ENOTSUP;
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}
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break;
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case VIDEO_BUF_TYPE_OUTPUT:
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data->output_buffer_cfg.pitchBytes = fmt->pitch;
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data->output_buffer_cfg.width = fmt->width;
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data->output_buffer_cfg.height = fmt->height;
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switch (fmt->pixelformat) {
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case VIDEO_PIX_FMT_RGB565:
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data->output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB565;
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break;
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case VIDEO_PIX_FMT_RGB24:
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data->output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB888;
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break;
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case VIDEO_PIX_FMT_XRGB32:
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case VIDEO_PIX_FMT_ARGB32:
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data->output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatARGB8888;
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break;
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default:
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return -ENOTSUP;
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}
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int mcux_pxp_set_ctrl(const struct device *dev, uint32_t id)
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{
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const struct mcux_pxp_config *const config = dev->config;
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struct mcux_pxp_data *data = dev->data;
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struct mcux_pxp_ctrls *ctrls = &data->ctrls;
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pxp_flip_mode_t flip = ctrls->hflip.val | ctrls->vflip.val;
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pxp_rotate_degree_t rotate = kPXP_Rotate0;
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ARG_UNUSED(id);
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switch (ctrls->rotation.val) {
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case 0:
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rotate = kPXP_Rotate0;
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break;
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case 90:
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rotate = kPXP_Rotate90;
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break;
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case 180:
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rotate = kPXP_Rotate180;
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break;
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case 270:
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rotate = kPXP_Rotate270;
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break;
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}
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PXP_SetRotateConfig(config->base, kPXP_RotateProcessSurface, rotate, flip);
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return 0;
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}
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static int mcux_pxp_enqueue(const struct device *dev, struct video_buffer *vbuf)
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{
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const struct mcux_pxp_config *const config = dev->config;
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struct mcux_pxp_data *data = dev->data;
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_CleanByRange((uint32_t)vbuf->buffer, vbuf->size);
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#endif
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switch (vbuf->type) {
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case VIDEO_BUF_TYPE_INPUT:
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k_fifo_put(&data->fifo_in_queued, vbuf);
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data->ps_buffer_cfg.swapByte = false;
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data->ps_buffer_cfg.bufferAddr = (uint32_t)vbuf->buffer;
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data->ps_buffer_cfg.bufferAddrU = 0U;
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data->ps_buffer_cfg.bufferAddrV = 0U;
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PXP_SetProcessSurfaceBufferConfig(config->base, &data->ps_buffer_cfg);
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break;
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case VIDEO_BUF_TYPE_OUTPUT:
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k_fifo_put(&data->fifo_out_queued, vbuf);
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data->output_buffer_cfg.interlacedMode = kPXP_OutputProgressive;
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data->output_buffer_cfg.buffer0Addr = (uint32_t)vbuf->buffer;
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data->output_buffer_cfg.buffer1Addr = 0U;
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PXP_SetOutputBufferConfig(config->base, &data->output_buffer_cfg);
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/* We only support a process surface that covers the full buffer */
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PXP_SetProcessSurfacePosition(config->base, 0U, 0U, data->output_buffer_cfg.width,
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data->output_buffer_cfg.height);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int mcux_pxp_dequeue(const struct device *dev, struct video_buffer **vbuf,
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k_timeout_t timeout)
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{
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struct mcux_pxp_data *data = dev->data;
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switch ((*vbuf)->type) {
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case VIDEO_BUF_TYPE_INPUT:
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*vbuf = k_fifo_get(&data->fifo_in_done, timeout);
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break;
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case VIDEO_BUF_TYPE_OUTPUT:
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*vbuf = k_fifo_get(&data->fifo_out_done, timeout);
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break;
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default:
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return -ENOTSUP;
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}
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if (*vbuf == NULL) {
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return -EAGAIN;
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}
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return 0;
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}
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static int mcux_pxp_set_stream(const struct device *dev, bool enable, enum video_buf_type type)
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{
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const struct mcux_pxp_config *const config = dev->config;
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struct mcux_pxp_data *data = dev->data;
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if (enable) {
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#ifdef CONFIG_HAS_MCUX_CACHE
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DCACHE_CleanByRange((uint32_t)data->ps_buffer_cfg.bufferAddr,
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data->output_buffer_cfg.pitchBytes *
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data->output_buffer_cfg.height);
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#endif
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PXP_Start(config->base);
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}
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return 0;
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}
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static DEVICE_API(video, mcux_pxp_driver_api) = {
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.get_caps = mcux_pxp_get_caps,
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.get_format = mcux_pxp_get_fmt,
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.set_format = mcux_pxp_set_fmt,
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.set_ctrl = mcux_pxp_set_ctrl,
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.enqueue = mcux_pxp_enqueue,
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.dequeue = mcux_pxp_dequeue,
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.set_stream = mcux_pxp_set_stream,
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};
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static int mcux_pxp_init(const struct device *const dev)
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{
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const struct mcux_pxp_config *const config = dev->config;
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struct mcux_pxp_data *data = dev->data;
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struct mcux_pxp_ctrls *ctrls = &data->ctrls;
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int ret;
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k_fifo_init(&data->fifo_in_queued);
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k_fifo_init(&data->fifo_out_queued);
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k_fifo_init(&data->fifo_in_done);
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k_fifo_init(&data->fifo_out_done);
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PXP_Init(config->base);
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PXP_SetProcessSurfaceBackGroundColor(config->base, 0U);
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/* Disable alpha surface and CSC1 */
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PXP_SetAlphaSurfacePosition(config->base, 0xFFFFU, 0xFFFFU, 0U, 0U);
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PXP_EnableCsc1(config->base, false);
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PXP_EnableInterrupts(config->base, kPXP_CompleteInterruptEnable);
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config->irq_config_func();
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ret = video_init_ctrl(
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&ctrls->rotation, dev, VIDEO_CID_ROTATE,
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(struct video_ctrl_range){.min = 0, .max = 270, .step = 90, .def = 0});
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if (ret) {
293+
return ret;
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}
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ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
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(struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
298+
if (ret) {
299+
return ret;
300+
}
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ret = video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
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(struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
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if (ret) {
305+
return ret;
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}
307+
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video_auto_cluster_ctrl(&ctrls->rotation, 3, false);
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return 0;
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}
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#define MCUX_PXP_INIT(inst) \
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static void mcux_pxp_irq_config_##inst(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), mcux_pxp_isr, \
317+
DEVICE_DT_INST_GET(inst), 0); \
318+
irq_enable(DT_INST_IRQN(inst)); \
319+
} \
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\
321+
static const struct mcux_pxp_config mcux_pxp_config_##inst = { \
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.base = (PXP_Type *)DT_INST_REG_ADDR(inst), \
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.irq_config_func = mcux_pxp_irq_config_##inst, \
324+
}; \
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\
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static struct mcux_pxp_data mcux_pxp_data_##inst; \
327+
\
328+
DEVICE_DT_INST_DEFINE(inst, &mcux_pxp_init, NULL, &mcux_pxp_data_##inst, \
329+
&mcux_pxp_config_##inst, POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, \
330+
&mcux_pxp_driver_api); \
331+
\
332+
VIDEO_DEVICE_DEFINE(pxp_##inst, DEVICE_DT_INST_GET(inst), NULL);
333+
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DT_INST_FOREACH_STATUS_OKAY(MCUX_PXP_INIT)

‎dts/arm/nxp/nxp_rt10xx.dtsi

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@@ -987,7 +987,6 @@
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reg = <0x402b4000 0x4000>;
988988
interrupts = <44 0>;
989989
status = "disabled";
990-
#dma-cells = <0>;
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};
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993992
sai1: sai@40384000 {

‎dts/arm/nxp/nxp_rt11xx.dtsi

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reg = <0x40814000 0x4000>;
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interrupts = <57 0>;
10651065
status = "disabled";
1066-
#dma-cells = <0>;
10671066
};
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10691068
iomuxcgpr: iomuxcgpr@400e4000 {

‎dts/bindings/video/nxp,pxp.yaml

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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description: NXP MCUX PxP
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9+
compatible: "nxp,pxp"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true

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