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soc: cyw20829: Use python script to generate app header
Instead of using app_header.c generate the app header using python script and merge with final binary post build Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
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8 files changed

+344
-146
lines changed

8 files changed

+344
-146
lines changed

‎boards/infineon/cyw920829m2evk_02/board.cmake

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,3 +18,5 @@ endif()
1818
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
1919
board_runner_args(jlink "--device=CYW20829_tm")
2020
include (${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
21+
22+
set_property(TARGET runners_yaml_props_target PROPERTY hex_file zephyr_merged.hex)

‎dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,9 @@
77

88
#include <mem.h>
99

10+
#define BOOTSTRAP_SIZE DT_SIZE_K(12)
11+
#define SRAM0_SIZE (DT_SIZE_K(256) - BOOTSTRAP_SIZE)
12+
1013
/ {
1114
cpus {
1215
#address-cells = <1>;
@@ -35,14 +38,46 @@
3538
};
3639

3740
sram0: memory@20000000 {
41+
#address-cells = <1>;
42+
#size-cells = <1>;
43+
3844
compatible = "mmio-sram";
39-
reg = <0x20000000 DT_SIZE_K(244)>;
45+
reg = <0x20000000 SRAM0_SIZE>;
46+
47+
/* SRAM aliased address path */
48+
sram_sahb: sram_bus_alias@20000000 {
49+
reg = <0x20000000 SRAM0_SIZE>; /* SAHB address */
50+
};
51+
52+
sram_cbus: sram_bus_alias@4000000 {
53+
reg = <0x04000000 SRAM0_SIZE>; /* CBUS address */
54+
};
4055
};
4156

57+
/* sram_bootstrap address calculation:
58+
* sram_sahb + sram_size (256k) - bootstrap size
59+
* (e.g. 0x20000000 + 0x40000 - 12K (0x3000) = 0x2003D000)
60+
*/
4261
sram_bootstrap: memory@2003D000 {
4362
compatible = "zephyr,memory-region", "mmio-sram";
4463
zephyr,memory-region = "BOOTSTRAP_RAM";
45-
reg = <0x2003D000 DT_SIZE_K(12)>;
64+
reg = <0x2003D000 BOOTSTRAP_SIZE>;
65+
};
66+
67+
qspi_flash: qspi_flash@40890000 {
68+
compatible = "infineon,cat1-qspi-flash";
69+
reg = <0x40890000 0x30000>;
70+
#address-cells = <1>;
71+
#size-cells = <1>;
72+
};
73+
74+
/* Flash aliased address path */
75+
flash_sahb: flash_bus_alias@60000000 {
76+
reg = <0x60000000 0x80000>; /* SAHB address */
77+
};
78+
79+
flash_cbus: flash_bus_alias@8000000 {
80+
reg = <0x08000000 0x80000>; /* CBUS address */
4681
};
4782

4883
soc {

‎soc/infineon/cat1b/cyw20829/CMakeLists.txt

Lines changed: 32 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
# Copyright (c) 2023 Cypress Semiconductor Corporation.
1+
# Copyright (c) 2024 Cypress Semiconductor Corporation.
22
# SPDX-License-Identifier: Apache-2.0
33

44
zephyr_sources(soc.c)
5-
zephyr_sources(app_header.c)
65
zephyr_sources(mpu_regions.c)
76
zephyr_include_directories(.)
87

@@ -19,3 +18,34 @@ zephyr_compile_definitions(CY_PDL_FLASH_BOOT)
1918

2019
# Use custome linker script
2120
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/linker.ld CACHE INTERNAL "")
21+
22+
# Get sram_bootstrap address and size
23+
dt_nodelabel(sram_bootstrap NODELABEL "sram_bootstrap")
24+
dt_reg_addr(bootstrap_dst_addr PATH ${sram_bootstrap})
25+
dt_reg_size(bootstrap_size PATH ${sram_bootstrap})
26+
27+
# Calculate the place in flash
28+
math(EXPR flash_addr_offset
29+
"${CONFIG_CYW20829_FLASH_SAHB_ADDR} + ${CONFIG_FLASH_LOAD_OFFSET} + ${CONFIG_ROM_START_OFFSET}"
30+
OUTPUT_FORMAT HEXADECIMAL
31+
)
32+
set(gen_app_header_args --flash_addr_offset ${flash_addr_offset})
33+
34+
# Generate platform specific header (TOC2, l1_desc, etc)
35+
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
36+
${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/infineon/cat1b/cyw20829/gen_app_header.py
37+
-p ${ZEPHYR_BINARY_DIR} -n ${KERNEL_NAME} ${gen_app_header_args}
38+
--bootstrap-size ${bootstrap_size}
39+
--bootstrap-dst-addr ${bootstrap_dst_addr}
40+
)
41+
42+
set(MERGED_FILE ${CMAKE_BINARY_DIR}/zephyr/zephyr_merged.hex CACHE PATH "merged hex")
43+
44+
# Merge platform specific header and zephyr image to a single binary.
45+
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
46+
COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py
47+
-o ${MERGED_FILE}
48+
${ZEPHYR_BINARY_DIR}/${KERNEL_NAME}.hex ${ZEPHYR_BINARY_DIR}/app_header.hex
49+
)
50+
51+
set_property(GLOBAL APPEND PROPERTY extra_post_build_byproducts ${MERGED_FILE})

‎soc/infineon/cat1b/cyw20829/Kconfig

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,19 @@ config SOC_SERIES_CYW20829
1616
select BUILD_OUTPUT_HEX
1717
select BUILD_OUTPUT_BIN
1818
select SOC_EARLY_INIT_HOOK
19+
20+
config CYW20829_FLASH_SAHB_ADDR
21+
hex
22+
default $(dt_nodelabel_reg_addr_hex,flash_sahb)
23+
24+
config CYW20829_FLASH_CBUS_ADDR
25+
hex
26+
default $(dt_nodelabel_reg_addr_hex,flash_cbus)
27+
28+
config CYW20829_SRAM_SAHB_ADDR
29+
hex
30+
default $(dt_nodelabel_reg_addr_hex,sram_sahb)
31+
32+
config CYW20829_SRAM_CBUS_ADDR
33+
hex
34+
default $(dt_nodelabel_reg_addr_hex,sram_cbus)

‎soc/infineon/cat1b/cyw20829/app_header.c

Lines changed: 0 additions & 45 deletions
This file was deleted.

‎soc/infineon/cat1b/cyw20829/bootstrap.ld

Lines changed: 15 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,13 @@
1-
/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
1+
/* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
22
* an affiliate of Cypress Semiconductor Corporation
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
SECTIONS
8-
{
9-
.app_header :
10-
{
11-
KEEP(*(.app_header))
12-
} > APP_HEADER_FLASH
13-
14-
/* Cortex-M33 bootstrap code area */
15-
.bootstrapText :
7+
/* Cortex-M33 bootstrap code area */
8+
bootstrap.text_lma = BS_CODE_LMA_CBUS;
9+
bootstrap.text_vma = BS_CODE_VMA_CBUS;
10+
.bootstrapText (bootstrap.text_vma) : AT (bootstrap.text_lma)
1611
{
1712
. = ALIGN(4);
1813
__bootstrapText_begin = .;
@@ -49,19 +44,23 @@ SECTIONS
4944

5045
. = ALIGN(4);
5146
__bootstrapText_end = .;
52-
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
47+
}
5348

54-
.bootstrapzero.table :
49+
bootstrap.zerotable.vma = (__bootstrapText_end);
50+
bootstrap.zerotable.lma = (bootstrap.text_lma + (__bootstrapText_end - __bootstrapText_begin));
51+
.bootstrapzero.table (bootstrap.zerotable.vma): AT (bootstrap.zerotable.lma)
5552
{
5653
. = ALIGN(4);
5754
__bootstrapzero_table_start__ = .;
5855
LONG (__bootstrap_bss_start__)
5956
LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
6057
. = ALIGN(4);
6158
__bootstrapzero_table_end__ = .;
62-
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
59+
}
6360

64-
.bootstrapData :
61+
bootstrap.data.vma = ((__bootstrapzero_table_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB); /* CBUS -> SAHB */
62+
bootstrap.data.lma = (bootstrap.zerotable.lma + (__bootstrapzero_table_end__ - __bootstrapzero_table_start__));
63+
.bootstrapData (bootstrap.data.vma): AT (bootstrap.data.lma)
6564
{
6665
__bootstrapData_start__ = .;
6766
. = ALIGN(4);
@@ -85,9 +84,9 @@ SECTIONS
8584

8685
. = ALIGN(4);
8786
__bootstrapData_end__ = .;
88-
} > BOOTSTRAP_RAM AT>BOOTSTRAP_FLASH
87+
} > BOOTSTRAP_RAM
8988

90-
.bootstrapBss (NOLOAD):
89+
.bootstrapBss (__bootstrapData_end__) (NOLOAD):
9190
{
9291
. = ALIGN(4);
9392
__bootstrap_bss_start__ = .;
@@ -111,4 +110,3 @@ SECTIONS
111110
. = ALIGN(4);
112111
__bootstrap_bss_end__ = .;
113112
} > BOOTSTRAP_RAM
114-
}

‎soc/infineon/cat1b/cyw20829/gen_app_header.py

Lines changed: 139 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,139 @@
1+
# Copyright (c) 2024 Cypress Semiconductor Corporation.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
import argparse
5+
import ctypes
6+
import sys
7+
from pathlib import Path
8+
9+
from intelhex import bin2hex
10+
11+
# Const
12+
TOC2_SIZE = 16
13+
L1_APP_DESCR_SIZE = 28
14+
L1_APP_DESCR_ADDR = 0x10
15+
DEBUG_CERT_ADDR = 0x0
16+
SERV_APP_DESCR_ADDR = 0x0
17+
18+
DEBUG = False
19+
20+
21+
# Define the structures
22+
class TOC2Data(ctypes.Structure):
23+
_fields_ = [
24+
("toc2_size", ctypes.c_uint32),
25+
("l1_app_descr_addr", ctypes.c_uint32),
26+
("service_app_descr_addr", ctypes.c_uint32),
27+
("debug_cert_addr", ctypes.c_uint32),
28+
]
29+
30+
31+
class L1Desc(ctypes.Structure):
32+
_fields_ = [
33+
("l1_app_descr_size", ctypes.c_uint32),
34+
("boot_strap_addr", ctypes.c_uint32),
35+
("boot_strap_dst_addr", ctypes.c_uint32),
36+
("boot_strap_size", ctypes.c_uint32),
37+
("smif_crypto_cfg", ctypes.c_uint8 * 12),
38+
("reserve", ctypes.c_uint8 * 4),
39+
]
40+
41+
42+
class SignHeader(ctypes.Structure):
43+
_fields_ = [
44+
("reserved", ctypes.c_uint8 * 32), # 32b for sign header
45+
]
46+
47+
48+
def generate_platform_headers(
49+
secure_lcs,
50+
output_path,
51+
project_name,
52+
bootstrap_size,
53+
bootstrap_dst_addr,
54+
flash_addr_offset,
55+
smif_config,
56+
):
57+
######################### Generate TOC2 #########################
58+
toc2_data = TOC2Data(
59+
toc2_size=TOC2_SIZE,
60+
l1_app_descr_addr=L1_APP_DESCR_ADDR,
61+
service_app_descr_addr=SERV_APP_DESCR_ADDR,
62+
debug_cert_addr=DEBUG_CERT_ADDR,
63+
)
64+
65+
###################### Generate L1_APP_DESCR ####################
66+
if secure_lcs:
67+
boot_strap_addr = 0x30 # Fix address for signed image
68+
else:
69+
boot_strap_addr = 0x50 # Fix address for un-signed image
70+
71+
l1_desc = L1Desc(
72+
l1_app_descr_size=L1_APP_DESCR_SIZE,
73+
boot_strap_addr=boot_strap_addr,
74+
boot_strap_dst_addr=int(bootstrap_dst_addr, 16),
75+
boot_strap_size=int(bootstrap_size, 16),
76+
)
77+
78+
if smif_config:
79+
with open(smif_config, 'rb') as binary_file:
80+
l1_desc.smif_crypto_cfg[0:] = binary_file.read()
81+
82+
# Write the structure to a binary file
83+
with open(Path(output_path) / 'app_header.bin', 'wb') as f:
84+
f.write(bytearray(toc2_data))
85+
f.write(bytearray(l1_desc))
86+
87+
if not secure_lcs:
88+
f.write(bytearray(SignHeader()))
89+
90+
# Generate hex from bin
91+
sys.exit(
92+
bin2hex(
93+
Path(output_path) / 'app_header.bin',
94+
Path(output_path) / 'app_header.hex',
95+
int(flash_addr_offset, 16),
96+
)
97+
)
98+
99+
100+
def main():
101+
parser = argparse.ArgumentParser(allow_abbrev=False)
102+
parser.add_argument(
103+
'-m',
104+
'--secure_lcs',
105+
required=False,
106+
type=bool,
107+
default=False,
108+
help='Use SECURE Life Cycle stage: True/False',
109+
)
110+
111+
parser.add_argument('-p', '--project-path', required=True, help='path to application artifacts')
112+
parser.add_argument('-n', '--project-name', required=True, help='Application name')
113+
parser.add_argument('-k', '--keys', required=False, help='Path to keys')
114+
115+
parser.add_argument('--bootstrap-size', required=False, help='Bootstrap size')
116+
parser.add_argument(
117+
'--bootstrap-dst-addr',
118+
required=False,
119+
help='Bootstrap destanation address. Should be in RAM (SAHB)',
120+
)
121+
122+
parser.add_argument('--flash_addr_offset', required=False, help='Flash offset')
123+
124+
parser.add_argument('-s', '--smif-config', required=False, help='smif config file')
125+
args = parser.parse_args()
126+
127+
generate_platform_headers(
128+
args.secure_lcs,
129+
args.project_path,
130+
args.project_name,
131+
args.bootstrap_size,
132+
args.bootstrap_dst_addr,
133+
args.flash_addr_offset,
134+
args.smif_config,
135+
)
136+
137+
138+
if __name__ == '__main__':
139+
main()

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