soc: microchip: sam: update MMU for sama7g5 XDMAC

When the XDMAC is activated in the DT, configure it's register region
with strong ordered, read and write access.

Signed-off-by: Tony Han <tony.han@microchip.com>

Author: TonyHan11

soc/microchip/sam/sama7g5/soc.c

@@ -15,6 +15,12 @@
 					       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),),	\
 			())
 
+#define MMU_REGION_XDMAC_DEFN(idx, n)								\
+		COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dma##n)),			\
+			(MMU_REGION_FLAT_ENTRY("xdmac"#n, XDMAC##n##_BASE_ADDRESS, 0x4000,	\
+					       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),),	\
+			())
+
 static const struct arm_mmu_region mmu_regions[] = {
 	MMU_REGION_FLAT_ENTRY("vectors", CONFIG_KERNEL_VM_BASE, 0x1000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
@@ -35,6 +41,8 @@ static const struct arm_mmu_region mmu_regions[] = {
 
 	MMU_REGION_FLAT_ENTRY("sckc", SCKC_BASE_ADDRESS, 0x4,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+
+	FOR_EACH_IDX(MMU_REGION_XDMAC_DEFN, (), 0, 1, 2)
 };
 
 const struct arm_mmu_config mmu_config = {