Skip to content

Commit 747d73c

Browse files
Alain Volmatdkalowsk
Alain Volmat
authored and
dkalowsk
committed
video: gc2145: use GC2145_REG_RESET macro for page selection
Help identify register page change by using GC2145_REG_RESET macro. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
1 parent 2f860e5 commit 747d73c

File tree

1 file changed

+44
-41
lines changed

1 file changed

+44
-41
lines changed

‎drivers/video/gc2145.c

Lines changed: 44 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,10 @@ LOG_MODULE_REGISTER(video_gc2145, CONFIG_VIDEO_LOG_LEVEL);
3333
#define GC2145_REG_SYNC_MODE_ROW_SWITCH 0x20
3434
#define GC2145_REG_RESET 0xFE
3535
#define GC2145_REG_SW_RESET 0x80
36-
#define GC2145_SET_P0_REGS 0x00
36+
#define GC2145_REG_RESET_P0_REGS 0x00
37+
#define GC2145_REG_RESET_P1_REGS 0x01
38+
#define GC2145_REG_RESET_P2_REGS 0x02
39+
#define GC2145_REG_RESET_P3_REGS 0x03
3740
#define GC2145_REG_CROP_ENABLE 0x90
3841
#define GC2145_CROP_SET_ENABLE 0x01
3942
#define GC2145_REG_BLANK_WINDOW_BASE 0x09
@@ -99,9 +102,9 @@ struct gc2145_reg {
99102
};
100103

101104
static const struct gc2145_reg default_regs[] = {
102-
{0xfe, 0xf0},
103-
{0xfe, 0xf0},
104-
{0xfe, 0xf0},
105+
{GC2145_REG_RESET, 0xf0},
106+
{GC2145_REG_RESET, 0xf0},
107+
{GC2145_REG_RESET, 0xf0},
105108
{0xfc, 0x06},
106109
{0xf6, 0x00},
107110
{0xf7, 0x1d},
@@ -111,7 +114,7 @@ static const struct gc2145_reg default_regs[] = {
111114
{0xf2, 0x00},
112115

113116
/* ISP settings */
114-
{0xfe, 0x00},
117+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
115118
{0x03, 0x04},
116119
{0x04, 0xe2},
117120

@@ -196,7 +199,7 @@ static const struct gc2145_reg default_regs[] = {
196199
{0xa2, 0x00},
197200

198201
/* BLK Settings */
199-
{0xfe, 0x00},
202+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
200203
{0x40, 0x42},
201204
{0x41, 0x00},
202205
{0x43, 0x5b},
@@ -225,14 +228,14 @@ static const struct gc2145_reg default_regs[] = {
225228
{0x72, 0xf0},
226229
{0x7e, 0x3c},
227230
{0x7f, 0x00},
228-
{0xfe, 0x02},
231+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
229232
{0x48, 0x15},
230233
{0x49, 0x00},
231234
{0x4b, 0x0b},
232-
{0xfe, 0x00},
235+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
233236

234237
/* AEC Settings */
235-
{0xfe, 0x01},
238+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
236239
{0x01, 0x04},
237240
{0x02, 0xc0},
238241
{0x03, 0x04},
@@ -254,26 +257,26 @@ static const struct gc2145_reg default_regs[] = {
254257
{0x20, 0x40},
255258
{0x22, 0x40},
256259
{0x23, 0x20},
257-
{0xfe, 0x02},
260+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
258261
{0x0f, 0x04},
259-
{0xfe, 0x01},
262+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
260263
{0x12, 0x30},
261264
{0x15, 0xb0},
262265
{0x10, 0x31},
263266
{0x3e, 0x28},
264267
{0x3f, 0xb0},
265268
{0x40, 0x90},
266269
{0x41, 0x0f},
267-
{0xfe, 0x02},
270+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
268271
{0x90, 0x6c},
269272
{0x91, 0x03},
270273
{0x92, 0xcb},
271274
{0x94, 0x33},
272275
{0x95, 0x84},
273276
{0x97, 0x65},
274277
{0xa2, 0x11},
275-
{0xfe, 0x00},
276-
{0xfe, 0x02},
278+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
279+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
277280
{0x80, 0xc1},
278281
{0x81, 0x08},
279282
{0x82, 0x05},
@@ -285,9 +288,9 @@ static const struct gc2145_reg default_regs[] = {
285288
{0x89, 0xb0},
286289
{0x8a, 0x30},
287290
{0x8b, 0x10},
288-
{0xfe, 0x01},
291+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
289292
{0x21, 0x04},
290-
{0xfe, 0x02},
293+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
291294
{0xa3, 0x50},
292295
{0xa4, 0x20},
293296
{0xa5, 0x40},
@@ -303,10 +306,10 @@ static const struct gc2145_reg default_regs[] = {
303306
{0x3d, 0x15},
304307
{0x4b, 0x06},
305308
{0x4c, 0x20},
306-
{0xfe, 0x00},
309+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
307310

308311
/* Gamma Control */
309-
{0xfe, 0x02},
312+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
310313
{0x10, 0x09},
311314
{0x11, 0x0d},
312315
{0x12, 0x13},
@@ -329,10 +332,10 @@ static const struct gc2145_reg default_regs[] = {
329332
{0x23, 0xf5},
330333
{0x24, 0xf9},
331334
{0x25, 0xff},
332-
{0xfe, 0x00},
335+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
333336
{0xc6, 0x20},
334337
{0xc7, 0x2b},
335-
{0xfe, 0x02},
338+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
336339
{0x26, 0x0f},
337340
{0x27, 0x14},
338341
{0x28, 0x19},
@@ -355,7 +358,7 @@ static const struct gc2145_reg default_regs[] = {
355358
{0x39, 0xf3},
356359
{0x3a, 0xf9},
357360
{0x3b, 0xff},
358-
{0xfe, 0x02},
361+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
359362
{0xd1, 0x32},
360363
{0xd2, 0x32},
361364
{0xd3, 0x40},
@@ -368,9 +371,9 @@ static const struct gc2145_reg default_regs[] = {
368371
{0xee, 0x00},
369372
{0xef, 0x3f},
370373
{0xd8, 0xd8},
371-
{0xfe, 0x01},
374+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
372375
{0x9f, 0x40},
373-
{0xfe, 0x01},
376+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
374377
{0xc2, 0x14},
375378
{0xc3, 0x0d},
376379
{0xc4, 0x0c},
@@ -428,7 +431,7 @@ static const struct gc2145_reg default_regs[] = {
428431
{0xa1, 0x80},
429432
{0xa2, 0x80},
430433

431-
{0xfe, 0x01},
434+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
432435
{0xdf, 0x0d},
433436
{0xdc, 0x25},
434437
{0xdd, 0x30},
@@ -440,8 +443,8 @@ static const struct gc2145_reg default_regs[] = {
440443
{0xe7, 0xa0},
441444
{0xe8, 0x90},
442445
{0xe9, 0xa0},
443-
{0xfe, 0x00},
444-
{0xfe, 0x01},
446+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
447+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
445448
{0x4f, 0x00},
446449
{0x4f, 0x00},
447450
{0x4b, 0x01},
@@ -681,8 +684,8 @@ static const struct gc2145_reg default_regs[] = {
681684
{0x79, 0x5e},
682685
{0x7a, 0x54},
683686
{0x7b, 0x58},
684-
{0xfe, 0x00},
685-
{0xfe, 0x02},
687+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
688+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
686689
{0xc0, 0x01},
687690
{0xc1, 0x44},
688691
{0xc2, 0xfd},
@@ -702,17 +705,17 @@ static const struct gc2145_reg default_regs[] = {
702705
{0xe3, 0x0c},
703706
{0xe4, 0x4b},
704707
{0xe5, 0xe0},
705-
{0xfe, 0x01},
708+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
706709
{0x9f, 0x40},
707-
{0xfe, 0x00},
710+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
708711

709712
/* Output Control */
710-
{0xfe, 0x02},
713+
{GC2145_REG_RESET, GC2145_REG_RESET_P2_REGS},
711714
{0x40, 0xbf},
712715
{0x46, 0xcf},
713-
{0xfe, 0x00},
716+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
714717

715-
{0xfe, 0x00},
718+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
716719
{0x05, 0x01},
717720
{0x06, 0x1C},
718721
{0x07, 0x00},
@@ -722,16 +725,16 @@ static const struct gc2145_reg default_regs[] = {
722725
{0x13, 0x00},
723726
{0x14, 0x00},
724727

725-
{0xfe, 0x01},
728+
{GC2145_REG_RESET, GC2145_REG_RESET_P1_REGS},
726729
{0x3c, 0x00},
727730
{0x3d, 0x04},
728-
{0xfe, 0x00},
731+
{GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS},
729732
{0x00, 0x00},
730733
};
731734

732735
static const struct gc2145_reg default_mipi_csi_regs[] = {
733736
/* Switch to page 3 */
734-
{0xfe, 0x03},
737+
{GC2145_REG_RESET, GC2145_REG_RESET_P3_REGS},
735738
{GC2145_REG_DPHY_MODE1, GC2145_DPHY_MODE1_CLK_EN |
736739
GC2145_DPHY_MODE1_LANE0_EN | GC2145_DPHY_MODE1_LANE1_EN |
737740
GC2145_DPHY_MODE1_CLK_LANE_P2S_SEL},
@@ -918,7 +921,7 @@ static int gc2145_set_window(const struct device *dev, uint16_t reg, uint16_t x,
918921
int ret;
919922
const struct gc2145_config *cfg = dev->config;
920923

921-
ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_SET_P0_REGS);
924+
ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS);
922925
if (ret < 0) {
923926
return ret;
924927
}
@@ -976,7 +979,7 @@ static int gc2145_set_output_format(const struct device *dev, int output_format)
976979
uint8_t old_value;
977980
const struct gc2145_config *cfg = dev->config;
978981

979-
ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_SET_P0_REGS);
982+
ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS);
980983
if (ret < 0) {
981984
return ret;
982985
}
@@ -1190,7 +1193,7 @@ static int gc2145_config_csi(const struct device *dev, uint32_t pixelformat,
11901193
return ret;
11911194
}
11921195

1193-
return gc2145_write_reg(&cfg->i2c, 0xfe, 0x0);
1196+
return gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS);
11941197
}
11951198

11961199
static int gc2145_set_fmt(const struct device *dev, struct video_format *fmt)
@@ -1268,7 +1271,7 @@ static int gc2145_set_stream_csi(const struct device *dev, bool enable)
12681271
const struct gc2145_config *cfg = dev->config;
12691272
int ret;
12701273

1271-
ret = gc2145_write_reg(&cfg->i2c, 0xfe, 0x03);
1274+
ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_REG_RESET_P3_REGS);
12721275
if (ret < 0) {
12731276
return ret;
12741277
}
@@ -1281,7 +1284,7 @@ static int gc2145_set_stream_csi(const struct device *dev, bool enable)
12811284
return ret;
12821285
}
12831286

1284-
return gc2145_write_reg(&cfg->i2c, 0xfe, 0x0);
1287+
return gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_REG_RESET_P0_REGS);
12851288
}
12861289

12871290
static int gc2145_set_stream(const struct device *dev, bool enable, enum video_buf_type type)

0 commit comments

Comments
 (0)