soc: renesas: rz: Update Renesas RZ/V2N, RZ/V2L according to RZ/V2H

tiennguyenzg · kartben · commit 7368758bd104 · 2025-06-24T14:22:43.000+02:00
Porting gp_renesas_isr_context variable used in FSP interrupt source
to unify with RZ/V2H and prevent build error since they share the same
hal_renesas source code.

Signed-off-by: Tien Nguyen &lt;tien.nguyen.zg@renesas.com&gt;
diff --git a/soc/renesas/rz/rzv2l/soc.c b/soc/renesas/rz/rzv2l/soc.c
@@ -14,6 +14,7 @@
 
 /* System core clock is set to 200 MHz after reset */
 uint32_t SystemCoreClock = 200000000;
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
 
 void soc_early_init_hook(void)
 {
diff --git a/soc/renesas/rz/rzv2n/soc.c b/soc/renesas/rz/rzv2n/soc.c
@@ -14,6 +14,7 @@
 
 /* System core clock is set to 200 MHz after reset */
 uint32_t SystemCoreClock = 200000000;
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];
 
 void soc_early_init_hook(void)
 {

Original file line number	Diff line number	Diff line change
`@@ -14,6 +14,7 @@`
`14`	`14`
`15`	`15`	`/* System core clock is set to 200 MHz after reset */`
`16`	`16`	`uint32_t SystemCoreClock = 200000000;`
	`17`	`+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES];`
`17`	`18`
`18`	`19`	`void soc_early_init_hook(void)`
`19`	`20`	`{`