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dts: arm: microchip: mec: Add MEC5 HAL based GIRQ information
Microchip MEC SoC's include an interrupt aggregator affecting the routing of interrupt to the ARM NVIC. IA can not be treated as a true second level interrupt controller. All interrupt sources with the exception of GPIOs and eSPI virtual wires can be routed by IA to individial NVIC inputs. Each bank of GPIOs and VWires are aggregated into a single NVIC input per bank. For the NVIC to receive the interrupt signal the respective GIRQ enable must be set. We attempted to add this informatation by encoding the DT irq property. This exeperiment failed due to how Zephyr builds the interrupt tables and MEC IA is not a true second level interrupt controller. Therefore, drivers for MEC peripherals need to GIRQ number and bit position to pass to HAL API's or if a driver is implemented in the linux style without using the full MEC HAL the GIRQ information is present in DT. Signed-off-by: Scott Worley <scott.worley@microchip.com>
1 parent c2d52c7 commit 719d539

13 files changed

+226
-76
lines changed

‎dts/arm/microchip/mec/mec5.dtsi

Lines changed: 117 additions & 41 deletions
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‎dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi

Lines changed: 0 additions & 25 deletions
This file was deleted.

‎dts/arm/microchip/mec/mec5_mec1743qlj.dtsi

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,11 +23,38 @@
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#include "mec5/mec5_gpspi_v2.dtsi"
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#include "mec5/mec5_eeprom_8kb.dtsi"
2525
#include "mec5/mec5_pkg176_pwms.dtsi"
26-
#include "mec5/mec5_pkg176_uarts.dtsi"
26+
27+
ps2_1: ps2@40009040 {
28+
reg = <0x40009040 0x40>;
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interrupts = <101 3>;
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girqs = <18 11>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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kscan0: kscan@40009c00 {
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reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
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girqs = <21 25>;
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status = "disabled";
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};
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uart2: uart@400f2c00 {
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reg = <0x400f2c00 0x400>;
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interrupts = <183 2>;
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girqs = <15 25>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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status = "disabled";
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};
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52+
uart3: uart@400f3000 {
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reg = <0x400f3000 0x400>;
54+
interrupts = <184 2>;
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girqs = <15 26>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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status = "disabled";
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};
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};

‎dts/arm/microchip/mec/mec5_mec1743qsz.dtsi

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,17 +23,28 @@
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#include "mec5/mec5_gpspi_v2.dtsi"
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#include "mec5/mec5_eeprom_8kb.dtsi"
2525

26+
ps2_1: ps2@40009040 {
27+
reg = <0x40009040 0x40>;
28+
interrupts = <101 3>;
29+
girqs = <18 11>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
34+
2635
kscan0: kscan@40009c00 {
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reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
38+
girqs = <21 25>;
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status = "disabled";
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};
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uart2: uart@400f2c00 {
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reg = <0x400f2c00 0x400>;
34-
interrupts = <183 1>;
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interrupts = <183 2>;
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girqs = <15 25>;
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clock-frequency = <1843200>;
36-
current-speed = <38400>;
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current-speed = <115200>;
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status = "disabled";
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};
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};

‎dts/arm/microchip/mec/mec5_mec1753qlj.dtsi

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,14 +23,39 @@
2323
#include "mec5/mec5_eeprom_8kb.dtsi"
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#include "mec5/mec5_gpspi_v2.dtsi"
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#include "mec5/mec5_pkg176_pwms.dtsi"
26-
#include "mec5/mec5_pkg176_uarts.dtsi"
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#include "mec5/mec5_i3c.dtsi"
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28+
ps2_1: ps2@40009040 {
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reg = <0x40009040 0x40>;
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interrupts = <101 3>;
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girqs = <18 11>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
36+
2937
kscan0: kscan@40009c00 {
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reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
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status = "disabled";
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};
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uart2: uart@400f2c00 {
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reg = <0x400f2c00 0x400>;
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interrupts = <183 2>;
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girqs = <15 25>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart3: uart@400f3000 {
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reg = <0x400f3000 0x400>;
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interrupts = <184 2>;
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girqs = <15 26>;
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clock-frequency = <1843200>;
57+
current-speed = <115200>;
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status = "disabled";
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};
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};
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};

‎dts/arm/microchip/mec/mec5_mec1753qsz.dtsi

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,28 @@
2424
#include "mec5/mec5_gpspi_v2.dtsi"
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#include "mec5/mec5_i3c.dtsi"
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27+
ps2_1: ps2@40009040 {
28+
reg = <0x40009040 0x40>;
29+
interrupts = <101 3>;
30+
girqs = <18 11>;
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#address-cells = <1>;
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#size-cells = <0>;
33+
status = "disabled";
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};
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kscan0: kscan@40009c00 {
2837
reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
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girqs = <21 25>;
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status = "disabled";
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};
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3343
uart2: uart@400f2c00 {
3444
reg = <0x400f2c00 0x400>;
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interrupts = <183 1>;
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interrupts = <183 2>;
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girqs = <15 25>;
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clock-frequency = <1843200>;
37-
current-speed = <38400>;
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current-speed = <115200>;
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status = "disabled";
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};
4051
};

‎dts/arm/microchip/mec/mec5_mech1723nlj.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@
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kscan0: kscan@40009c00 {
2828
reg = <0x40009c00 0x18>;
2929
interrupts = <135 0>;
30+
girqs = <21 25>;
3031
status = "disabled";
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};
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};

‎dts/arm/microchip/mec/mec5_mech1723nsz.dtsi

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@
2626
kscan0: kscan@40009c00 {
2727
reg = <0x40009c00 0x18>;
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interrupts = <135 0>;
29+
girqs = <21 25>;
2930
status = "disabled";
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};
3132
};

‎dts/bindings/gpio/microchip,mec5-gpio.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ description: Microchip MEC5 GPIO
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compatible: "microchip,mec5-gpio"
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8-
include: [gpio-controller.yaml, base.yaml]
8+
include: ["gpio-controller.yaml", "base.yaml", "microchip,dmec-ecia-girq.yaml"]
99

1010
properties:
1111
reg:

‎dts/bindings/interrupt-controller/microchip,dmec-ecia-girq.yaml

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
description: Microchip DEC/MEC series External Interrupt Aggregator GIRQ
2+
3+
compatible: "microchip,dmec-ecia-girq"
4+
5+
include: base.yaml
6+
7+
properties:
8+
girqs:
9+
type: array
10+
required: true
11+
description: |
12+
Many DEC/MEC periperals interrupt signals are direct capable. The signals are
13+
connected to bits in a GIRQ. Each GIRQ is composed of 5 32-bit registers:
14+
status(latched or r/w1-c), set-enable, clr-enable, and result (read-only).
15+
The read-only result register bits are the bitwise AND of status and enable.
16+
Direct mode routes the individual result register bits to NVIC inputs. If
17+
direct mode is disable by setting direct mode bit to 0 in the EC subsystem
18+
interrupt control register then the result register outputs are OR'd together
19+
and the OR'd result is connected to an NVIC input based on GIRQ number.
20+
To enable an interrupt a driver must know:
21+
a. NVIC input number and priority from the interrupts property
22+
b. GIRQ number and bit position from the girqs property
23+
The number of entries in interrupts and girqs should be the same in a DT node.

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