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khoa-nguyen-18khoa-nguyen-18
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drivers: mipi_dsi: Update the modification of FSP migration
Update modification of FSP 6.0.0 for dsi_renesas_ra Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
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1 file changed

+41
-30
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‎drivers/mipi_dsi/dsi_renesas_ra.c

Lines changed: 41 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -227,8 +227,18 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
227227
#define RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(n) \
228228
static const mipi_phy_timing_t mipi_phy_##n##_timing = { \
229229
.t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF), \
230-
.t_clk_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), 0, 0xFF), \
231-
.t_hs_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), 0, 0xFF), \
230+
.dphytim2_b = \
231+
{ \
232+
.t_clk_prep = \
233+
CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), \
234+
0, 0xFF), \
235+
}, \
236+
.dphytim3_b = \
237+
{ \
238+
.t_hs_prep = \
239+
CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), \
240+
0, 0xFF), \
241+
}, \
232242
.t_lp_exit = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_lp_exit), 0, 0xFF), \
233243
.dphytim4_b = \
234244
{ \
@@ -261,6 +271,7 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
261271
}, \
262272
.lp_divisor = CLAMP(DT_INST_PROP(n, lp_divisor), 1, 32) - 1, \
263273
.p_timing = &mipi_phy_##n##_timing, \
274+
.dsi_mode = true, /* enable DSI mode, disable CSI mode */ \
264275
}; \
265276
\
266277
mipi_phy_ctrl_t mipi_phy_##n##_ctrl; \
@@ -309,31 +320,31 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
309320
.dsi_ferr.irq = DT_INST_IRQ_BY_NAME(id, ferr, irq), \
310321
.dsi_ppi.ipl = DT_INST_IRQ_BY_NAME(id, ppi, priority), \
311322
.dsi_ppi.irq = DT_INST_IRQ_BY_NAME(id, ppi, irq), \
312-
.dsi_rxie = R_DSILINK_RXIER_BTAREND_Msk | R_DSILINK_RXIER_LRXHTO_Msk | \
313-
R_DSILINK_RXIER_TATO_Msk | R_DSILINK_RXIER_RXRESP_Msk | \
314-
R_DSILINK_RXIER_RXEOTP_Msk | R_DSILINK_RXIER_RXTE_Msk | \
315-
R_DSILINK_RXIER_RXACK_Msk | R_DSILINK_RXIER_EXTEDET_Msk | \
316-
R_DSILINK_RXIER_MLFERR_Msk | R_DSILINK_RXIER_ECCERRM_Msk | \
317-
R_DSILINK_RXIER_UNEXERR_Msk | R_DSILINK_RXIER_WCERR_Msk | \
318-
R_DSILINK_RXIER_CRCERR_Msk | R_DSILINK_RXIER_IBERR_Msk | \
319-
R_DSILINK_RXIER_RXOVFERR_Msk | R_DSILINK_RXIER_PRTOERR_Msk | \
320-
R_DSILINK_RXIER_NORESERR_Msk | R_DSILINK_RXIER_RSIZEERR_Msk | \
321-
R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk, \
322-
.dsi_ferrie = R_DSILINK_FERRIER_HTXTO_Msk | R_DSILINK_FERRIER_LRXHTO_Msk | \
323-
R_DSILINK_FERRIER_TATO_Msk | R_DSILINK_FERRIER_ESCENT_Msk | \
324-
R_DSILINK_FERRIER_SYNCESC_Msk | R_DSILINK_FERRIER_CTRL_Msk | \
325-
R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk, \
326-
.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk, \
327-
.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk, \
328-
.dsi_sqch0ie = R_DSILINK_SQCH0IER_AACTFIN_Msk | R_DSILINK_SQCH0IER_ADESFIN_Msk | \
329-
R_DSILINK_SQCH0IER_TXIBERR_Msk | R_DSILINK_SQCH0IER_RXFERR_Msk | \
330-
R_DSILINK_SQCH0IER_RXFAIL_Msk | R_DSILINK_SQCH0IER_RXPFAIL_Msk | \
331-
R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk, \
332-
.dsi_sqch1ie = R_DSILINK_SQCH1IER_AACTFIN_Msk | R_DSILINK_SQCH1IER_ADESFIN_Msk | \
333-
R_DSILINK_SQCH1IER_SIZEERR_Msk | R_DSILINK_SQCH1IER_TXIBERR_Msk | \
334-
R_DSILINK_SQCH1IER_RXFERR_Msk | R_DSILINK_SQCH1IER_RXFAIL_Msk | \
335-
R_DSILINK_SQCH1IER_RXPFAIL_Msk | R_DSILINK_SQCH1IER_RXCORERR_Msk | \
336-
R_DSILINK_SQCH1IER_RXAKE_Msk, \
323+
.dsi_rxie = R_MIPI_DSI_RXIER_BTAREND_Msk | R_MIPI_DSI_RXIER_LRXHTO_Msk | \
324+
R_MIPI_DSI_RXIER_TATO_Msk | R_MIPI_DSI_RXIER_RXRESP_Msk | \
325+
R_MIPI_DSI_RXIER_RXEOTP_Msk | R_MIPI_DSI_RXIER_RXTE_Msk | \
326+
R_MIPI_DSI_RXIER_RXACK_Msk | R_MIPI_DSI_RXIER_EXTEDET_Msk | \
327+
R_MIPI_DSI_RXIER_MLFERR_Msk | R_MIPI_DSI_RXIER_ECCERRM_Msk | \
328+
R_MIPI_DSI_RXIER_UNEXERR_Msk | R_MIPI_DSI_RXIER_WCERR_Msk | \
329+
R_MIPI_DSI_RXIER_CRCERR_Msk | R_MIPI_DSI_RXIER_IBERR_Msk | \
330+
R_MIPI_DSI_RXIER_RXOVFERR_Msk | R_MIPI_DSI_RXIER_PRTOERR_Msk | \
331+
R_MIPI_DSI_RXIER_NORESERR_Msk | R_MIPI_DSI_RXIER_RSIZEERR_Msk | \
332+
R_MIPI_DSI_RXIER_ECCERRS_Msk | R_MIPI_DSI_RXIER_RXAKE_Msk, \
333+
.dsi_ferrie = R_MIPI_DSI_FERRIER_HTXTO_Msk | R_MIPI_DSI_FERRIER_LRXHTO_Msk | \
334+
R_MIPI_DSI_FERRIER_TATO_Msk | R_MIPI_DSI_FERRIER_ESCENT_Msk | \
335+
R_MIPI_DSI_FERRIER_SYNCESC_Msk | R_MIPI_DSI_FERRIER_CTRL_Msk | \
336+
R_MIPI_DSI_FERRIER_CLP0_Msk | R_MIPI_DSI_FERRIER_CLP1_Msk, \
337+
.dsi_plie = R_MIPI_DSI_PLIER_DLULPENT_Msk | R_MIPI_DSI_PLIER_DLULPEXT_Msk, \
338+
.dsi_vmie = R_MIPI_DSI_VMIER_VBUFUDF_Msk | R_MIPI_DSI_VMIER_VBUFOVF_Msk, \
339+
.dsi_sqch0ie = R_MIPI_DSI_SQCH0IER_AACTFIN_Msk | R_MIPI_DSI_SQCH0IER_ADESFIN_Msk | \
340+
R_MIPI_DSI_SQCH0IER_TXIBERR_Msk | R_MIPI_DSI_SQCH0IER_RXFERR_Msk | \
341+
R_MIPI_DSI_SQCH0IER_RXFAIL_Msk | R_MIPI_DSI_SQCH0IER_RXPFAIL_Msk | \
342+
R_MIPI_DSI_SQCH0IER_RXCORERR_Msk | R_MIPI_DSI_SQCH0IER_RXAKE_Msk, \
343+
.dsi_sqch1ie = R_MIPI_DSI_SQCH1IER_AACTFIN_Msk | R_MIPI_DSI_SQCH1IER_ADESFIN_Msk | \
344+
R_MIPI_DSI_SQCH1IER_SIZEERR_Msk | R_MIPI_DSI_SQCH1IER_TXIBERR_Msk | \
345+
R_MIPI_DSI_SQCH1IER_RXFERR_Msk | R_MIPI_DSI_SQCH1IER_RXFAIL_Msk | \
346+
R_MIPI_DSI_SQCH1IER_RXPFAIL_Msk | \
347+
R_MIPI_DSI_SQCH1IER_RXCORERR_Msk | R_MIPI_DSI_SQCH1IER_RXAKE_Msk, \
337348
}; \
338349
\
339350
static const struct mipi_dsi_renesas_ra_config ra_config_##id = { \
@@ -355,9 +366,9 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
355366
.vertical_sync_polarity = 1, \
356367
.horizontal_sync_polarity = 1, \
357368
.video_mode_delay = DT_INST_PROP(id, video_mode_delay), \
358-
.hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk, \
359-
.hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk, \
360-
.hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk, \
369+
.hsa_no_lp = R_MIPI_DSI_VMSET0R_HSANOLP_Msk, \
370+
.hbp_no_lp = R_MIPI_DSI_VMSET0R_HBPNOLP_Msk, \
371+
.hfp_no_lp = R_MIPI_DSI_VMSET0R_HFPNOLP_Msk, \
361372
.ulps_wakeup_period = DT_INST_PROP(id, ulps_wakeup_period), \
362373
.continuous_clock = (1), \
363374
.hs_tx_timeout = 0, \

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