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Alain Volmat
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clock_control: stm32: add handling of clocks for the stm32mp13
Add enabled_clock, on / off and configure support for the clocks of the stm32mp13. Describes the peripheral clock source selection. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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3 files changed

+223
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‎drivers/clock_control/clock_stm32_ll_mp13.c

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,29 @@
1717
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
1818
#include <zephyr/sys/util.h>
1919

20+
/** @brief Verifies clock is part of active clock configuration */
21+
int enabled_clock(uint32_t src_clk)
22+
{
23+
if ((src_clk == STM32_SRC_HSE && IS_ENABLED(STM32_HSE_ENABLED)) ||
24+
(src_clk == STM32_SRC_HSI && IS_ENABLED(STM32_HSI_ENABLED)) ||
25+
(src_clk == STM32_SRC_LSE && IS_ENABLED(STM32_LSE_ENABLED)) ||
26+
(src_clk == STM32_SRC_LSI && IS_ENABLED(STM32_LSI_ENABLED)) ||
27+
(src_clk == STM32_SRC_PLL1_P && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
28+
(src_clk == STM32_SRC_PLL2_P && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
29+
(src_clk == STM32_SRC_PLL2_Q && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
30+
(src_clk == STM32_SRC_PLL2_R && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
31+
(src_clk == STM32_SRC_PLL3_P && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
32+
(src_clk == STM32_SRC_PLL3_Q && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
33+
(src_clk == STM32_SRC_PLL3_R && IS_ENABLED(STM32_PLL3_R_ENABLED)) ||
34+
(src_clk == STM32_SRC_PLL4_P && IS_ENABLED(STM32_PLL4_P_ENABLED)) ||
35+
(src_clk == STM32_SRC_PLL4_Q && IS_ENABLED(STM32_PLL4_Q_ENABLED)) ||
36+
(src_clk == STM32_SRC_PLL4_R && IS_ENABLED(STM32_PLL4_R_ENABLED))) {
37+
return 0;
38+
}
39+
40+
return -ENOTSUP;
41+
}
42+
2043
static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
2144
{
2245
struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
@@ -57,6 +80,32 @@ static int stm32_clock_control_off(const struct device *dev, clock_control_subsy
5780
return 0;
5881
}
5982

83+
static int stm32_clock_control_configure(const struct device *dev,
84+
clock_control_subsys_t sub_system,
85+
void *data)
86+
{
87+
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
88+
int err;
89+
90+
ARG_UNUSED(dev);
91+
ARG_UNUSED(data);
92+
93+
err = enabled_clock(pclken->bus);
94+
if (err < 0) {
95+
/* Attempt to configure a src clock not available or not valid */
96+
return err;
97+
}
98+
99+
sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
100+
STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
101+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
102+
sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
103+
STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
104+
STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
105+
106+
return 0;
107+
}
108+
60109
static int stm32_clock_control_get_subsys_rate(const struct device *dev,
61110
clock_control_subsys_t sub_system, uint32_t *rate)
62111
{
@@ -99,10 +148,37 @@ static int stm32_clock_control_get_subsys_rate(const struct device *dev,
99148
return 0;
100149
}
101150

151+
static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
152+
clock_control_subsys_t sub_system)
153+
{
154+
struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
155+
156+
ARG_UNUSED(dev);
157+
158+
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
159+
/* Gated clocks */
160+
if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
161+
== pclken->enr) {
162+
return CLOCK_CONTROL_STATUS_ON;
163+
} else {
164+
return CLOCK_CONTROL_STATUS_OFF;
165+
}
166+
} else {
167+
/* Domain clock sources */
168+
if (enabled_clock(pclken->bus) == 0) {
169+
return CLOCK_CONTROL_STATUS_ON;
170+
} else {
171+
return CLOCK_CONTROL_STATUS_OFF;
172+
}
173+
}
174+
}
175+
102176
static DEVICE_API(clock_control, stm32_clock_control_api) = {
103177
.on = stm32_clock_control_on,
104178
.off = stm32_clock_control_off,
105179
.get_rate = stm32_clock_control_get_subsys_rate,
180+
.configure = stm32_clock_control_configure,
181+
.get_status = stm32_clock_control_get_status,
106182
};
107183

108184
static void set_up_fixed_clock_sources(void)

‎include/zephyr/drivers/clock_control/stm32_clock_control.h

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,8 @@
179179
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \
180180
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \
181181
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \
182-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay)
182+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) || \
183+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32mp13_pll_clock, okay)
183184
#define STM32_PLL_ENABLED 1
184185
#define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m)
185186
#define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n)
@@ -215,7 +216,8 @@
215216

216217
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \
217218
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \
218-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay)
219+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) || \
220+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32mp13_pll_clock, okay)
219221
#define STM32_PLL2_ENABLED 1
220222
#define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m)
221223
#define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n)
@@ -235,7 +237,8 @@
235237

236238
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \
237239
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \
238-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay)
240+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) || \
241+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32mp13_pll_clock, okay)
239242
#define STM32_PLL3_ENABLED 1
240243
#define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m)
241244
#define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n)
@@ -251,6 +254,20 @@
251254
#define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1)
252255
#endif
253256

257+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32mp13_pll_clock, okay)
258+
#define STM32_PLL4_ENABLED 1
259+
#define STM32_PLL4_M_DIVISOR DT_PROP(DT_NODELABEL(pll4), div_m)
260+
#define STM32_PLL4_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll4), mul_n)
261+
#define STM32_PLL4_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_p)
262+
#define STM32_PLL4_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_p, 1)
263+
#define STM32_PLL4_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_q)
264+
#define STM32_PLL4_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_q, 1)
265+
#define STM32_PLL4_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), div_r)
266+
#define STM32_PLL4_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll4), div_r, 1)
267+
#define STM32_PLL4_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll4), fracn)
268+
#define STM32_PLL4_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll4), fracn, 1)
269+
#endif
270+
254271
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay)
255272
#define STM32_PLL_ENABLED 1
256273
#define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre)

‎include/zephyr/dt-bindings/clock/stm32mp13_clock.h

Lines changed: 127 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,24 @@
88

99
#include "stm32_common_clocks.h"
1010

11+
/** System clock */
12+
/* defined in stm32_common_clocks.h */
13+
/** Fixed clocks */
14+
#define STM32_SRC_HSE (STM32_SRC_LSI + 1)
15+
#define STM32_SRC_HSI (STM32_SRC_HSE + 1)
16+
17+
/** PLL outputs */
18+
#define STM32_SRC_PLL1_P (STM32_SRC_HSI + 1)
19+
#define STM32_SRC_PLL2_P (STM32_SRC_PLL1_P + 1)
20+
#define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
21+
#define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1)
22+
#define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1)
23+
#define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
24+
#define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
25+
#define STM32_SRC_PLL4_P (STM32_SRC_PLL3_R + 1)
26+
#define STM32_SRC_PLL4_Q (STM32_SRC_PLL4_P + 1)
27+
#define STM32_SRC_PLL4_R (STM32_SRC_PLL4_Q + 1)
28+
1129
/** Bus clocks */
1230
#define STM32_CLOCK_BUS_APB1 0x700
1331
#define STM32_CLOCK_BUS_APB2 0x708
@@ -24,4 +42,113 @@
2442
#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_APB1
2543
#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB6
2644

45+
/** @brief Device domain clocks selection helpers */
46+
#define MCO1CFGR_REG 0x460
47+
#define MCO2CFGR_REG 0x464
48+
#define I2C12CKSELR_REG 0x600
49+
#define I2C345CKSELR_REG 0x604
50+
#define SPI2S1CKSELR_REG 0x608
51+
#define SPI2S23CKSELR_REG 0x60c
52+
#define SPI45CKSELR_REG 0x610
53+
#define UART12CKSELR_REG 0x614
54+
#define UART35CKSELR_REG 0x618
55+
#define UART4CKSELR_REG 0x61c
56+
#define UART6CKSELR_REG 0x620
57+
#define UART78CKSELR_REG 0x624
58+
#define LPTIM1CKSELR_REG 0x628
59+
#define LPTIM23CKSELR_REG 0x62c
60+
#define LPTIM45CKSELR_REG 0x630
61+
#define SAI1CKSELR_REG 0x634
62+
#define SAI2CKSELR_REG 0x638
63+
#define FDCANCKSELR_REG 0x63c
64+
#define SPDIFCKSELR_REG 0x640
65+
#define ADC12CKSELR_REG 0x644
66+
#define SDMMC12CKSELR_REG 0x648
67+
#define ETH12CKSELR_REG 0x64c
68+
#define USBCKSELR_REG 0x650
69+
#define QSPICKSELR_REG 0x654
70+
#define FMCCKSELR_REG 0x658
71+
#define RNG1CKSELR_REG 0x65c
72+
#define STGENCKSELR_REG 0x660
73+
#define DCMIPPCKSELR_REG 0x664
74+
#define SAESCKSELR_REG 0x668
75+
76+
/** MCO1CFGR / MCO2CFGR devices */
77+
#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO1CFGR_REG)
78+
#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO1CFGR_REG)
79+
#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, MCO2CFGR_REG)
80+
#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0xf, 4, MCO2CFGR_REG)
81+
82+
#define MCO_ENABLE_BIT BIT(12)
83+
84+
/* MCO1 source */
85+
#define MCO1_SEL_HSI 0
86+
#define MCO1_SEL_HSE 1
87+
#define MCO1_SEL_CSI 2
88+
#define MCO1_SEL_LSI 3
89+
#define MCO1_SEL_LSE 4
90+
91+
/* MCO2 source */
92+
#define MCO2_SEL_MPU 0
93+
#define MCO2_SEL_AXI 1
94+
#define MCO2_SEL_MLAHB 2
95+
#define MCO2_SEL_PLL4 3
96+
#define MCO2_SEL_HSE 4
97+
#define MCO2_SEL_HSI 5
98+
99+
/* MCO prescaler : division factor */
100+
#define MCO_PRE_DIV_1 0
101+
#define MCO_PRE_DIV_2 1
102+
#define MCO_PRE_DIV_3 2
103+
#define MCO_PRE_DIV_4 3
104+
#define MCO_PRE_DIV_5 4
105+
#define MCO_PRE_DIV_6 5
106+
#define MCO_PRE_DIV_7 6
107+
#define MCO_PRE_DIV_8 7
108+
#define MCO_PRE_DIV_9 8
109+
#define MCO_PRE_DIV_10 9
110+
#define MCO_PRE_DIV_11 10
111+
#define MCO_PRE_DIV_12 11
112+
#define MCO_PRE_DIV_13 12
113+
#define MCO_PRE_DIV_14 13
114+
#define MCO_PRE_DIV_15 14
115+
#define MCO_PRE_DIV_16 15
116+
117+
#define I2C12_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C12CKSELR_REG)
118+
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, I2C345CKSELR_REG)
119+
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, I2C345CKSELR_REG)
120+
#define I2C5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 6, I2C345CKSELR_REG)
121+
#define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S1CKSELR_REG)
122+
#define SPI23_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI2S23CKSELR_REG)
123+
#define SPI4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SPI45CKSELR_REG)
124+
#define SPI5_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SPI45CKSELR_REG)
125+
#define UART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART12CKSELR_REG)
126+
#define UART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, UART12CKSELR_REG)
127+
#define UART35_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART35CKSELR_REG)
128+
#define UART4_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART4CKSELR_REG)
129+
#define UART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART6CKSELR_REG)
130+
#define UART78_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, UART78CKSELR_REG)
131+
#define LPTIME1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM1CKSELR_REG)
132+
#define LPTIME2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM23CKSELR_REG)
133+
#define LPTIME3_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, LPTIM23CKSELR_REG)
134+
#define LPTIME45_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, LPTIM45CKSELR_REG)
135+
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI1CKSELR_REG)
136+
#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SAI2CKSELR_REG)
137+
#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FDCANCKSELR_REG)
138+
#define SPDIF_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SPDIFCKSELR_REG)
139+
#define ADC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ADC12CKSELR_REG)
140+
#define ADC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 2, ADC12CKSELR_REG)
141+
#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 0, SDMMC12CKSELR_REG)
142+
#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x7, 3, SDMMC12CKSELR_REG)
143+
#define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, ETH12CKSELR_REG)
144+
#define ETH2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 8, ETH12CKSELR_REG)
145+
#define USBPHY_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, USBCKSELR_REG)
146+
#define USBOTG_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x1, 4, USBCKSELR_REG)
147+
#define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, QSPICKSELR_REG)
148+
#define FMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, FMCCKSELR_REG)
149+
#define RNG1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, RNG1CKSELR_REG)
150+
#define STGEN_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, STGENCKSELR_REG)
151+
#define DCMIPP_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, DCMIPPCKSELR_REG)
152+
#define SAES_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 0, SAESCKSELR_REG)
153+
27154
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */

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