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TonyHan11dkalowsk
TonyHan11
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dkalowsk
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dts: microchip: sam: add I2C (FLEXCOM submodule) nodes to sama7g5.dtsi
Each of the 12 FLEXCOM instances supports working in TWI (I2C) mode. Signed-off-by: Tony Han <tony.han@microchip.com>
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‎dts/arm/microchip/sam/sama7g5.dtsi

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@@ -8,6 +8,7 @@
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#include <arm/armv7-a.dtsi>
99
#include <mem.h>
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#include <zephyr/dt-bindings/clock/microchip_sam_pmc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
@@ -53,6 +54,18 @@
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ranges = <0x0 0xe1818000 0x800>;
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status = "disabled";
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57+
i2c0: i2c0@600 {
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compatible = "atmel,sam-i2c-twi";
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reg = <0x600 0x200>;
60+
clock-frequency = <I2C_BITRATE_STANDARD>;
61+
interrupt-parent = <&gic>;
62+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
63+
#address-cells = <1>;
64+
#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
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status = "disabled";
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};
68+
5669
usart0: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -71,6 +84,18 @@
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ranges = <0x0 0xe181c000 0x800>;
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status = "disabled";
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i2c1: i2c1@600 {
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compatible = "atmel,sam-i2c-twi";
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reg = <0x600 0x200>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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status = "disabled";
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};
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usart1: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -89,6 +114,18 @@
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ranges = <0x0 0xe1820000 0x800>;
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status = "disabled";
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i2c2: i2c2@600 {
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compatible = "atmel,sam-i2c-twi";
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reg = <0x600 0x200>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
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status = "disabled";
127+
};
128+
92129
usart2: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -107,6 +144,18 @@
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ranges = <0x0 0xe1824000 0x800>;
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status = "disabled";
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i2c3: i2c3@600 {
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compatible = "atmel,sam-i2c-twi";
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reg = <0x600 0x200>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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status = "disabled";
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};
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usart3: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -125,6 +174,18 @@
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ranges = <0x0 0xe2018000 0x800>;
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status = "disabled";
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i2c4: i2c4@600 {
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compatible = "atmel,sam-i2c-twi";
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reg = <0x600 0x200>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
181+
interrupt-parent = <&gic>;
182+
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
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status = "disabled";
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};
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128189
usart4: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -143,6 +204,18 @@
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ranges = <0x0 0xe201c000 0x800>;
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status = "disabled";
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i2c5: i2c5@600 {
208+
compatible = "atmel,sam-i2c-twi";
209+
reg = <0x600 0x200>;
210+
clock-frequency = <I2C_BITRATE_STANDARD>;
211+
interrupt-parent = <&gic>;
212+
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
213+
#address-cells = <1>;
214+
#size-cells = <0>;
215+
clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
216+
status = "disabled";
217+
};
218+
146219
usart5: serial@200 {
147220
compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -161,6 +234,18 @@
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ranges = <0x0 0xe2020000 0x800>;
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status = "disabled";
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237+
i2c6: i2c6@600 {
238+
compatible = "atmel,sam-i2c-twi";
239+
reg = <0x600 0x200>;
240+
clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupt-parent = <&gic>;
242+
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
243+
#address-cells = <1>;
244+
#size-cells = <0>;
245+
clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
246+
status = "disabled";
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};
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164249
usart6: serial@200 {
165250
compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -179,6 +264,18 @@
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ranges = <0x0 0xe2024000 0x800>;
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status = "disabled";
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i2c7: i2c7@600 {
268+
compatible = "atmel,sam-i2c-twi";
269+
reg = <0x600 0x200>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
271+
interrupt-parent = <&gic>;
272+
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
273+
#address-cells = <1>;
274+
#size-cells = <0>;
275+
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
276+
status = "disabled";
277+
};
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182279
usart7: serial@200 {
183280
compatible = "atmel,sam-usart";
184281
reg = <0x200 0x200>;
@@ -197,6 +294,18 @@
197294
ranges = <0x0 0xe2818000 0x800>;
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status = "disabled";
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297+
i2c8: i2c8@600 {
298+
compatible = "atmel,sam-i2c-twi";
299+
reg = <0x600 0x200>;
300+
clock-frequency = <I2C_BITRATE_STANDARD>;
301+
interrupt-parent = <&gic>;
302+
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
303+
#address-cells = <1>;
304+
#size-cells = <0>;
305+
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
306+
status = "disabled";
307+
};
308+
200309
usart8: serial@200 {
201310
compatible = "atmel,sam-usart";
202311
reg = <0x200 0x200>;
@@ -215,6 +324,18 @@
215324
ranges = <0x0 0xe281c000 0x800>;
216325
status = "disabled";
217326

327+
i2c9: i2c9@600 {
328+
compatible = "atmel,sam-i2c-twi";
329+
reg = <0x600 0x200>;
330+
clock-frequency = <I2C_BITRATE_STANDARD>;
331+
interrupt-parent = <&gic>;
332+
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
333+
#address-cells = <1>;
334+
#size-cells = <0>;
335+
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
336+
status = "disabled";
337+
};
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218339
usart9: serial@200 {
219340
compatible = "atmel,sam-usart";
220341
reg = <0x200 0x200>;
@@ -233,6 +354,18 @@
233354
ranges = <0x0 0xe2820000 0x800>;
234355
status = "disabled";
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357+
i2c10: i2c10@600 {
358+
compatible = "atmel,sam-i2c-twi";
359+
reg = <0x600 0x200>;
360+
clock-frequency = <I2C_BITRATE_STANDARD>;
361+
interrupt-parent = <&gic>;
362+
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
363+
#address-cells = <1>;
364+
#size-cells = <0>;
365+
clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
366+
status = "disabled";
367+
};
368+
236369
usart10: serial@200 {
237370
compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
@@ -251,6 +384,18 @@
251384
ranges = <0x0 0xe2824000 0x800>;
252385
status = "disabled";
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387+
i2c11: i2c11@600 {
388+
compatible = "atmel,sam-i2c-twi";
389+
reg = <0x600 0x200>;
390+
clock-frequency = <I2C_BITRATE_STANDARD>;
391+
interrupt-parent = <&gic>;
392+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
393+
#address-cells = <1>;
394+
#size-cells = <0>;
395+
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
396+
status = "disabled";
397+
};
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254399
usart11: serial@200 {
255400
compatible = "atmel,sam-usart";
256401
reg = <0x200 0x200>;

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