drivers: ethernet: phy: microchip_vsc8541: use default speeds

- use default speeds
- implement configure link
- support half duplex
- use defines from mii.h

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

drivers/ethernet/phy/phy_microchip_vsc8541.c

@@ -16,6 +16,9 @@ LOG_MODULE_REGISTER(microchip_vsc8541, CONFIG_PHY_LOG_LEVEL);
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/drivers/gpio.h>
 
+#include "phy_mii.h"
+#include "phy_common.h"
+
 /* phy page selectors */
 #define PHY_PAGE_0 0x00 /* main registers space active */
 #define PHY_PAGE_1 0x01 /* reg 16 - 30 will be redirected to ext. register space 1 */
@@ -26,25 +29,14 @@ LOG_MODULE_REGISTER(microchip_vsc8541, CONFIG_PHY_LOG_LEVEL);
 #define PHY_REG(page, reg) ((page << 8) | (reg << 0))
 
 /* Generic Register */
-#define PHY_REG_PAGE0_BMCR            PHY_REG(PHY_PAGE_0, 0x00)
-#define PHY_REG_PAGE0_BMSR            PHY_REG(PHY_PAGE_0, 0x01)
-#define PHY_REG_PAGE0_ID1             PHY_REG(PHY_PAGE_0, 0x02)
-#define PHY_REG_PAGE0_ID2             PHY_REG(PHY_PAGE_0, 0x03)
-#define PHY_REG_PAGE0_ADV             PHY_REG(PHY_PAGE_0, 0x04)
-#define PHY_REG_LPA                   0x05
-#define PHY_REG_EXP                   0x06
-#define PHY_REG_PAGE0_CTRL1000        PHY_REG(PHY_PAGE_0, 0x09)
-#define PHY_REG_PAGE0_STAT1000        PHY_REG(0, 0x0A)
-#define PHY_REG_MMD_CTRL              0x0D
-#define PHY_REG_MMD_DATA              0x0E
-#define PHY_REG_STAT1000_EXT1         0x0F
 #define PHY_REG_PAGE0_STAT100         PHY_REG(PHY_PAGE_0, 0x10)
 #define PHY_REG_PAGE0_STAT1000_EXT2   PHY_REG(PHY_PAGE_0, 0x11)
 #define PHY_REG_AUX_CTRL              0x12
 #define PHY_REG_PAGE0_ERROR_COUNTER_1 PHY_REG(0, 0x13)
 #define PHY_REG_PAGE0_ERROR_COUNTER_2 PHY_REG(0, 0x14)
 #define PHY_REG_PAGE0_EXT_CTRL_STAT   PHY_REG(PHY_PAGE_0, 0x16)
 #define PHY_REG_PAGE0_EXT_CONTROL_1   PHY_REG(PHY_PAGE_0, 0x17)
+#define PHY_REG_PAGE0_EXT_DEV_AUX     PHY_REG(PHY_PAGE_0, 0x1C)
 #define PHY_REG_LED_MODE              0x1d
 
 #define PHY_REG_PAGE_SELECTOR 0x1F
@@ -54,19 +46,7 @@ LOG_MODULE_REGISTER(microchip_vsc8541, CONFIG_PHY_LOG_LEVEL);
 #define PHY_REG_PAGE2_RGMII_CONTROL  PHY_REG(PHY_PAGE_2, 0x14)
 #define PHY_REG_PAGE2_MAC_IF_CONTROL PHY_REG(PHY_PAGE_2, 0x1b)
 
-/* selected bits in registers */
-#define BMCR_RESET     (1 << 15)
-#define BMCR_LOOPBACK  (1 << 14)
-#define BMCR_ANENABLE  (1 << 12)
-#define BMCR_ANRESTART (1 << 9)
-#define BMCR_FULLDPLX  (1 << 8)
-#define BMCR_SPEED10   ((0 << 13) | (0 << 6))
-#define BMCR_SPEED100  ((1 << 13) | (0 << 6))
-#define BMCR_SPEED1000 ((0 << 13) | (1 << 6))
-
-#define BMCR_SPEEDMASK ((1 << 13) | (1 << 6))
-
-#define BMSR_LSTATUS (1 << 2)
+#define PHY_REG_PAGE0_EXT_DEV_AUX_DUPLEX BIT(5)
 
 enum vsc8541_interface {
 	VSC8541_MII,
@@ -85,6 +65,7 @@ struct mc_vsc8541_config {
 	uint8_t addr;
 	const struct device *mdio_dev;
 	enum vsc8541_interface microchip_interface_type;
+	enum phy_link_speed default_speeds;
 	uint8_t rgmii_rx_clk_delay;
 	uint8_t rgmii_tx_clk_delay;
 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
@@ -123,11 +104,11 @@ static int phy_mc_vsc8541_verify_phy_id(const struct device *dev)
 	uint16_t phy_id_1;
 	uint16_t phy_id_2;
 
-	if (0 != phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_ID1, (uint32_t *)&phy_id_1)) {
+	if (0 != phy_mc_vsc8541_read(dev, MII_PHYID1R, (uint32_t *)&phy_id_1)) {
 		return -EINVAL;
 	}
 
-	if (0 != phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_ID2, (uint32_t *)&phy_id_2)) {
+	if (0 != phy_mc_vsc8541_read(dev, MII_PHYID2R, (uint32_t *)&phy_id_2)) {
 		return -EINVAL;
 	}
 
@@ -210,7 +191,7 @@ static int phy_mc_vsc8541_reset(const struct device *dev)
 	}
 
 	/* software reset */
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_BMCR, MII_BMCR_RESET);
+	ret = phy_mc_vsc8541_write(dev, MII_BMCR, MII_BMCR_RESET);
 	if (ret) {
 		return ret;
 	}
@@ -219,47 +200,17 @@ static int phy_mc_vsc8541_reset(const struct device *dev)
 	uint32_t reg = 0;
 
 	do {
-		phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMCR, &reg);
-	} while (reg & BMCR_RESET);
-
-	/* forced MDI-X */
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE1_EXT_MODE_CTRL, (3 << 2));
-	if (ret) {
-		return ret;
-	}
+		phy_mc_vsc8541_read(dev, MII_BMCR, &reg);
+	} while (reg & MII_BMCR_RESET);
 
 	/* configure the RGMII clk delay */
 	reg = 0x0;
 	/* RX_CLK delay */
 	reg |= (cfg->rgmii_rx_clk_delay << 4);
 	/* TX_CLK delay */
 	reg |= (cfg->rgmii_tx_clk_delay << 0);
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE2_RGMII_CONTROL, reg);
-	if (ret) {
-		return ret;
-	}
-
-	/* we use limited advertising, to force gigabit speed */
-	/* initial version of this driver supports only 1GB/s */
-
-	/* 1000MBit/s + AUTO */
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_ADV, (1 << 8) | (1 << 6) | 0x01);
-	if (ret) {
-		return ret;
-	}
-
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_CTRL1000, (1 << 12) | (1 << 11) | (1 << 9));
-	if (ret) {
-		return ret;
-	}
 
-	/* start auto negotiation */
-	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
-	if (ret) {
-		return ret;
-	}
-
-	return ret;
+	return phy_mc_vsc8541_write(dev, PHY_REG_PAGE2_RGMII_CONTROL, reg);
 }
 
 /**
@@ -271,12 +222,13 @@ static int phy_mc_vsc8541_reset(const struct device *dev)
 static int phy_mc_vsc8541_get_speed(const struct device *dev, struct phy_link_state *state)
 {
 	int ret;
-	uint32_t status;
+	uint32_t aux_status;
 	uint32_t link10_status;
 	uint32_t link100_status;
 	uint32_t link1000_status;
+	bool is_duplex;
 
-	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMSR, &status);
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_EXT_DEV_AUX, &aux_status);
 	if (ret) {
 		return ret;
 	}
@@ -296,41 +248,41 @@ static int phy_mc_vsc8541_get_speed(const struct device *dev, struct phy_link_st
 		return ret;
 	}
 
-	if ((status & (1 << 2)) == 0) {
-		/* no link */
-		state->speed = LINK_HALF_10BASE;
-	}
-
-	if ((status & (1 << 5)) == 0) {
-		/* auto negotiation not yet complete */
-		state->speed = LINK_HALF_10BASE;
-	}
+	is_duplex = (aux_status & PHY_REG_PAGE0_EXT_DEV_AUX_DUPLEX) != 0;
 
 	if ((link1000_status & (1 << 12))) {
-		state->speed = LINK_FULL_1000BASE;
+		state->speed = is_duplex ? LINK_FULL_1000BASE : LINK_HALF_1000BASE;
 	}
 	if (link100_status & (1 << 12)) {
-		state->speed = LINK_FULL_100BASE;
+		state->speed = is_duplex ? LINK_FULL_100BASE : LINK_HALF_100BASE;
 	}
 	if (link10_status & (1 << 6)) {
-		state->speed = LINK_FULL_10BASE;
+		state->speed = is_duplex ? LINK_FULL_10BASE : LINK_HALF_10BASE;
 	}
 
 	return 0;
 }
 
+static int phy_mc_vsc8541_cfg_link(const struct device *dev, enum phy_link_speed adv_speeds,
+				   enum phy_cfg_link_flag flags)
+{
+	if (flags & PHY_FLAG_AUTO_NEGOTIATION_DISABLED) {
+		LOG_ERR("Disabling auto-negotiation is not supported by this driver");
+		return -ENOTSUP;
+	}
+
+	return phy_mii_cfg_link_autoneg(dev, adv_speeds, true);
+}
+
 /**
  * @brief Initializes the phy and starts the link monitor
  *
  */
 static int phy_mc_vsc8541_init(const struct device *dev)
 {
 	struct mc_vsc8541_data *data = dev->data;
+	struct mc_vsc8541_config *cfg = dev->config;
 
-	data->cb = NULL;
-	data->cb_data = NULL;
-	data->state.is_up = false;
-	data->state.speed = LINK_HALF_10BASE;
 	data->active_page = -1;
 
 	/* Reset PHY */
@@ -349,6 +301,8 @@ static int phy_mc_vsc8541_init(const struct device *dev)
 
 	k_thread_name_set(&data->link_monitor_thread, "phy-link-mon");
 
+	phy_mc_vsc8541_cfg_link(dev, cfg->default_speeds, 0);
+
 	return 0;
 }
 
@@ -363,37 +317,35 @@ static int phy_mc_vsc8541_get_link(const struct device *dev, struct phy_link_sta
 	int ret;
 	uint32_t reg_sr;
 	uint32_t reg_cr;
+	bool hasLink;
+	bool auto_negotiation_finished = true;
 
-	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMSR, &reg_sr);
+	ret = phy_mc_vsc8541_read(dev, MII_BMSR, &reg_sr);
 	if (ret) {
 		return ret;
 	}
 
-	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMCR, &reg_cr);
+	ret = phy_mc_vsc8541_read(dev, MII_BMCR, &reg_cr);
 	if (ret) {
 		return ret;
 	}
 
-	uint32_t hasLink = reg_sr & (1 << 2) ? 1 : 0;
+	hasLink = (reg_sr & MII_BMSR_LINK_STATUS) != 0;
 
-	uint32_t auto_negotiation_finished;
-
-	if (reg_cr & (BMCR_ANENABLE)) {
+	if (reg_cr & MII_BMCR_AUTONEG_ENABLE) {
 		/* auto negotiation active; update status */
-		auto_negotiation_finished = reg_sr & (1 << 5) ? 1 : 0;
-	} else {
-		auto_negotiation_finished = 1;
+		auto_negotiation_finished = (reg_sr & MII_BMSR_AUTONEG_COMPLETE) != 0;
 	}
 
 	if (hasLink & auto_negotiation_finished) {
-		state->is_up = 1;
+		state->is_up = true;
 		ret = phy_mc_vsc8541_get_speed(dev, state);
 		if (ret) {
 			return ret;
 		}
 	} else {
-		state->is_up = 0;
-		state->speed = LINK_HALF_10BASE;
+		state->is_up = false;
+		state->speed = 0;
 	}
 
 	return 0;
@@ -556,6 +508,7 @@ static DEVICE_API(ethphy, mc_vsc8541_phy_api) = {
 		.microchip_interface_type = DT_INST_ENUM_IDX(n, microchip_interface_type),         \
 		.rgmii_rx_clk_delay = DT_INST_PROP(n, microchip_rgmii_rx_clk_delay),               \
 		.rgmii_tx_clk_delay = DT_INST_PROP(n, microchip_rgmii_tx_clk_delay),               \
+		.default_speeds = PHY_INST_GENERATE_DEFAULT_SPEEDS(n),				   \
 		RESET_GPIO(n) INTERRUPT_GPIO(n)};                                                  \
                                                                                                    \
 	static struct mc_vsc8541_data mc_vsc8541_##n##_data;                                       \

dts/bindings/ethernet/phy/microchip,vsc8541-phy.yaml

@@ -42,3 +42,7 @@ properties:
     description: |
       Used to configure the TX clock delay for RGMII interface. The value can be
       0 to 7. Refer to the datasheet for more details on the delay settings.
+
+  default-speeds:
+    default: ["10BASE Half-Duplex", "10BASE Full-Duplex", "100BASE Half-Duplex",
+              "100BASE Full-Duplex", "1000BASE Half-Duplex", "1000BASE Full-Duplex"]