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TonyHan11dkalowsk
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dts: microchip: sam: add all USART (FLEXCOM submodule) to sama7g5.dtsi
SAMA7G5 has 12 FLEXCOM instances and each of them supports working in USART mode. Signed-off-by: Tony Han <tony.han@microchip.com>
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dts/arm/microchip/sam/sama7g5.dtsi

Lines changed: 198 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,60 @@
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#clock-cells = <1>;
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};
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flx0: flexcom@e1818000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe1818000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe1818000 0x800>;
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status = "disabled";
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usart0: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx1: flexcom@e181c000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe181c000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe181c000 0x800>;
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status = "disabled";
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usart1: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx2: flexcom@e1820000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe1820000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe1820000 0x800>;
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status = "disabled";
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usart2: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx3: flexcom@e1824000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe1824000 0x200>;
@@ -63,6 +117,150 @@
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};
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};
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flx4: flexcom@e2018000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2018000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2018000 0x800>;
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status = "disabled";
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usart4: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx5: flexcom@e201c000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe201c000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe201c000 0x800>;
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status = "disabled";
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usart5: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx6: flexcom@e2020000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2020000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2020000 0x800>;
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status = "disabled";
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usart6: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx7: flexcom@e2024000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2024000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2024000 0x800>;
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status = "disabled";
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usart7: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx8: flexcom@e2818000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2818000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2818000 0x800>;
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status = "disabled";
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usart8: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx9: flexcom@e281c000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe281c000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe281c000 0x800>;
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status = "disabled";
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usart9: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx10: flexcom@e2820000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2820000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2820000 0x800>;
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status = "disabled";
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usart10: serial@200 {
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compatible = "atmel,sam-usart";
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reg = <0x200 0x200>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 48>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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flx11: flexcom@e2824000 {
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compatible = "microchip,sam-flexcom";
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reg = <0xe2824000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0xe2824000 0x800>;
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status = "disabled";
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usart11: serial@200 {
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compatible = "atmel,sam-usart";
256+
reg = <0x200 0x200>;
257+
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
258+
interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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status = "disabled";
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};
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};
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gic: interrupt-controller@e8c11000 {
67265
compatible = "arm,gic-v2", "arm,gic";
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reg = <0xe8c11000 0x1000>, <0xe8c12000 0x100>;

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