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arch: microblaze: Early Boot Sequence
Internal references: FWRIVERHD-4969 Signed-off-by: Alp Sayin <alpsayin@gmail.com>
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arch/microblaze/core/crt0.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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MicroBlaze Vector Map for standalone executables
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Address Vector type Label
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------- ----------- ------
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# 0x00 # (-- IMM --)
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# 0x04 # Reset _start
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# 0x08 # (-- IMM --)
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# 0x0c # Software Exception _exception_handler
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# 0x10 # (-- IMM --)
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# 0x14 # Hardware Interrupt _interrupt_handler
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# 0x18 # (-- IMM --)
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# 0x1C # Breakpoint Exception (-- Don't Care --)
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# 0x20 # (-- IMM --)
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# 0x24 # Hardware Exception _hw_exception_handler
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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/* imports */
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GTEXT(_PrepC)
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.section .vectors.sw_exception, "ax"
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.balign 4
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_vector_sw_exception:
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brai _exception_handler_entry
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.section .vectors.interrupt, "ax"
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.balign 4
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_vector_interrupt:
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brai _interrupt_handler
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.section .vectors.hw_exception, "ax"
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.balign 4
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_vector_hw_exception:
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brai _exception_handler_entry
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.section .text
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.globl _start
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.balign 4
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.ent _start
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.type _start, @function
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_start:
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/* Set the Small Data Anchors and the stack pointer */
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ori r13, r0, _SDA_BASE_
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ori r2, r0, _SDA2_BASE_
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/* Initialize global pointer with the linker variable we set */
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ori r20, r0, _gp
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#ifdef CONFIG_INIT_STACKS
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/* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
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ori r3, r0, z_interrupt_stacks
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addik r4, r3, __z_interrupt_stack_SIZEOF
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ori r5, r0, 0xaaaaaaaa
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/* Populate z_interrupt_stacks with 0xaaaaaaaa */
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aa_loop:
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sw r5, r0, r3
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addik r3, r3, 4
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cmpu r6, r3, r4
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bnei r6, aa_loop
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#endif
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/* Load the initial stack */
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ori r1, r0, z_interrupt_stacks
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addik r1, r1, __z_interrupt_stack_SIZEOF
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/* Initialize BSS and run program */
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/* clear SBSS */
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addi r6, r0, __sbss_start
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addi r7, r0, __sbss_end
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rsub r18, r6, r7
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blei r18, .Lendsbss
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.Lloopsbss:
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swi r0, r6, 0
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addi r6, r6, 4
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rsub r18, r6, r7
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bgti r18, .Lloopsbss
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.Lendsbss:
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/* bss region is cleaned up by _PrepC */
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addi r6, r0, 0 /* Initialize argc = 0 */
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addi r7, r0, 0 /* Set envp = NULL*/
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brlid r15, _PrepC /* Execute the program */
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addi r5, r0, 0 /* Set argv = NULL */
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/* Call exit with the return value of main */
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brlid r15, _exit
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addik r5, r3, 0
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/* Control does not reach here */
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.end _start

arch/microblaze/core/prep_c.c

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/cache.h>
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#include <zephyr/irq.h>
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#include <zephyr/init.h>
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#include <kernel_internal.h>
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/**
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*
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* @brief Prepare to and run C code
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*
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* This routine prepares for the execution of and runs C code.
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*
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* @return N/A
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*/
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void _PrepC(void)
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{
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microblaze_disable_interrupts();
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#if defined(CONFIG_CACHE_MANAGEMENT)
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#if defined(CONFIG_ICACHE)
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cache_instr_enable();
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#endif
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#if defined(CONFIG_DCACHE)
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cache_data_enable();
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#endif
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#endif
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z_bss_zero();
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z_cstart();
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CODE_UNREACHABLE;
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}
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/**
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*
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* @brief Re-enable interrupts after kernel is initialised
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*
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* @return 0
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*/
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static int interrupt_init_post_kernel(void)
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{
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microblaze_enable_interrupts();
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return 0;
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}
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SYS_INIT(interrupt_init_post_kernel, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

arch/microblaze/core/reset.S

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/*
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* Copyright (c) 2023 Advanced Micro Devices, Inc. (AMD)
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* Copyright (c) 2023 Alp Sayin <alpsayin@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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// import
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GTEXT(_start)
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// export
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GTEXT(__start)
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.globl _reset
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.section .vectors.reset, "ax"
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.balign 4
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.ent _reset
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.type _reset, @function
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_reset:
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__start:
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brai _start
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.end _reset

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