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LucasTamborkartben
LucasTambor
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kartben
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drivers: gpio: Add LP GPIO
Add LP GPIO support for LP Core Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
1 parent 9a6f116 commit 5d74f78

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7 files changed

+245
-2
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7 files changed

+245
-2
lines changed

‎boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig

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@@ -17,3 +17,4 @@ CONFIG_CBPRINTF_NANO=y
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# Build
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CONFIG_SIZE_OPTIMIZATIONS=y
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CONFIG_BUSYWAIT_CPU_LOOPS_PER_USEC=4

‎drivers/gpio/CMakeLists.txt

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@@ -117,6 +117,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_XEC_V2 gpio_mchp_xec_v2.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XLNX_AXI gpio_xlnx_axi.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XLNX_PS gpio_xlnx_ps.c gpio_xlnx_ps_bank.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XMC4XXX gpio_xmc4xxx.c)
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zephyr_library_sources_ifdef(CONFIG_LPGPIO_ESP32 gpio_esp32_lp.c)
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# zephyr-keep-sorted-stop
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# zephyr-keep-sorted-start

‎drivers/gpio/Kconfig.esp32

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@@ -6,6 +6,13 @@
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config GPIO_ESP32
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bool "ESP32 GPIO"
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default y
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depends on DT_HAS_ESPRESSIF_ESP32_GPIO_ENABLED
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depends on DT_HAS_ESPRESSIF_ESP32_GPIO_ENABLED && !SOC_ESP32C6_LPCORE
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help
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Enables the ESP32 GPIO driver
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config LPGPIO_ESP32
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bool "ESP32 Low Power GPIO"
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default y
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depends on DT_HAS_ESPRESSIF_ESP32_GPIO_ENABLED && SOC_ESP32C6_LPCORE
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help
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Enables the ESP32 GPIO driver

‎drivers/gpio/gpio_esp32_lp.c

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/*
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* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_lpgpio
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#include <soc.h>
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <hal/rtc_io_hal.h>
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#include <soc/rtc_io_periph.h>
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#include <ulp_lp_core_interrupts.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
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struct gpio_esp32_lp_config {
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struct gpio_driver_config drv_cfg;
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lp_io_dev_t *const lp_io_dev;
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};
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struct gpio_esp32_lp_data {
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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void ulp_lp_core_lp_io_intr_handler(void)
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{
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uint32_t intr_status = rtcio_ll_get_interrupt_status();
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const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(lp_gpio));
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struct gpio_esp32_lp_data *data = dev->data;
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rtcio_ll_clear_interrupt_status();
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gpio_fire_callbacks(&data->cb, dev, intr_status);
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}
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bool lp_gpio_is_valid(uint32_t pin)
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{
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return rtc_io_num_map[pin] >= 0;
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}
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static int gpio_esp32_lp_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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if (!lp_gpio_is_valid(pin)) {
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LOG_ERR("Selected LP IO pin is not valid.");
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return -EINVAL;
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}
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rtcio_hal_function_select(pin, RTCIO_FUNC_RTC);
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if (flags & GPIO_OUTPUT) {
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rtcio_hal_set_direction(pin, RTC_GPIO_MODE_OUTPUT_ONLY);
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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rtcio_hal_set_level(pin, 1);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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rtcio_hal_set_level(pin, 0);
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}
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} else if (flags & GPIO_INPUT) {
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rtcio_hal_set_direction(pin, RTC_GPIO_MODE_INPUT_ONLY);
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}
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return 0;
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}
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static int gpio_esp32_lp_port_get_raw(const struct device *port, uint32_t *value)
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{
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const struct gpio_esp32_lp_config *const cfg = port->config;
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*value = cfg->lp_io_dev->in.val;
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return 0;
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}
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static int gpio_esp32_lp_port_set_masked_raw(const struct device *port, uint32_t mask,
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uint32_t value)
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{
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const struct gpio_esp32_lp_config *const cfg = port->config;
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cfg->lp_io_dev->out_data.val = (cfg->lp_io_dev->out_data.val & ~mask) | (mask & value);
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return 0;
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}
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static int gpio_esp32_lp_port_set_bits_raw(const struct device *port, uint32_t pins)
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{
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const struct gpio_esp32_lp_config *const cfg = port->config;
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cfg->lp_io_dev->out_data_w1ts.val = pins;
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return 0;
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}
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static int gpio_esp32_lp_port_clear_bits_raw(const struct device *port, uint32_t pins)
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{
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const struct gpio_esp32_lp_config *const cfg = port->config;
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cfg->lp_io_dev->out_data_w1tc.val = pins;
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return 0;
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}
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static int gpio_esp32_lp_port_toggle_bits(const struct device *port, uint32_t pins)
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{
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const struct gpio_esp32_lp_config *const cfg = port->config;
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cfg->lp_io_dev->out_data.val ^= pins;
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return 0;
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}
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static int lp_gpio_convert_int_type(enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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if (mode == GPIO_INT_MODE_DISABLED) {
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return RTCIO_INTR_DISABLE;
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}
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if (mode == GPIO_INT_MODE_LEVEL) {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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return RTCIO_INTR_LOW_LEVEL;
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case GPIO_INT_TRIG_HIGH:
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return RTCIO_INTR_HIGH_LEVEL;
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default:
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return -EINVAL;
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}
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} else { /* edge interrupts */
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switch (trig) {
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case GPIO_INT_TRIG_HIGH:
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return RTCIO_INTR_POSEDGE;
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case GPIO_INT_TRIG_LOW:
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return RTCIO_INTR_NEGEDGE;
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case GPIO_INT_TRIG_BOTH:
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return RTCIO_INTR_ANYEDGE;
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default:
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return -EINVAL;
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}
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}
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/* Any other type of interrupt triggering is invalid. */
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return -EINVAL;
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}
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static int gpio_esp32_lp_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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int intr_trig_mode = lp_gpio_convert_int_type(mode, trig);
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if (!lp_gpio_is_valid(pin)) {
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LOG_ERR("Selected LP IO pin is not valid.");
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return -EINVAL;
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}
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rtcio_ll_clear_interrupt_status();
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ulp_lp_core_intr_enable();
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rtcio_ll_intr_enable(pin, intr_trig_mode);
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return 0;
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}
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static int gpio_esp32_lp_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_esp32_lp_data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static uint32_t gpio_esp32_lp_get_pending_int(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return rtcio_ll_get_interrupt_status();
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}
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static int gpio_esp32_lp_init(const struct device *dev)
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{
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return 0;
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}
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static DEVICE_API(gpio, gpio_esp32_lp_driver_api) = {
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.pin_configure = gpio_esp32_lp_configure,
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.port_get_raw = gpio_esp32_lp_port_get_raw,
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.port_set_masked_raw = gpio_esp32_lp_port_set_masked_raw,
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.port_set_bits_raw = gpio_esp32_lp_port_set_bits_raw,
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.port_clear_bits_raw = gpio_esp32_lp_port_clear_bits_raw,
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.port_toggle_bits = gpio_esp32_lp_port_toggle_bits,
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.pin_interrupt_configure = gpio_esp32_lp_pin_interrupt_configure,
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.manage_callback = gpio_esp32_lp_manage_callback,
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.get_pending_int = gpio_esp32_lp_get_pending_int
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};
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static struct gpio_esp32_lp_data gpio_esp32_lp_data_0;
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static struct gpio_esp32_lp_config gpio_esp32_lp_cfg = {
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.drv_cfg = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(DT_NODELABEL(lp_gpio)),
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},
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.lp_io_dev = (lp_io_dev_t *)DT_REG_ADDR(DT_NODELABEL(lp_gpio)),
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(lp_gpio), gpio_esp32_lp_init, NULL, &gpio_esp32_lp_data_0,
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&gpio_esp32_lp_cfg, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,
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&gpio_esp32_lp_driver_api);

‎dts/bindings/gpio/espressif,esp32-lpgpio.yaml

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# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: ESP32 Low Power GPIO controller for LP Core
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compatible: "espressif,esp32-lpgpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

‎dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi

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status = "disabled";
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};
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lp_gpio: gpio@600b2000 {
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compatible = "espressif,esp32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x600b2000 DT_SIZE_K(4)>;
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ngpios = <8>;
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};
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};
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};

‎west.yml

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groups:
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- hal
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- name: hal_espressif
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revision: dbc28ad4c1bdcdb25e79ca225cb5528a75d8dc91
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revision: c811e7e58ecb2574a4ae6a1c777015185cdaf199
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path: modules/hal/espressif
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west-commands: west/west-commands.yml
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groups:

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