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drivers: spi: litex: remove core_ prefix
remove `core_` prefix from code and register names, got dropped in litex in enjoy-digital/litex#2253 Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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+37
-37
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2 files changed

+37
-37
lines changed

‎drivers/spi/spi_litex_litespi.c

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -13,22 +13,22 @@ LOG_MODULE_REGISTER(spi_litex_litespi);
1313
#include <zephyr/sys/byteorder.h>
1414
#include "spi_litex_common.h"
1515

16-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET 0x0
17-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
18-
#define SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET 0x2
16+
#define SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET 0x0
17+
#define SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET 0x1
18+
#define SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET 0x2
1919

20-
#define SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET 0x0
21-
#define SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET 0x1
20+
#define SPIFLASH_MASTER_STATUS_TX_READY_OFFSET 0x0
21+
#define SPIFLASH_MASTER_STATUS_RX_READY_OFFSET 0x1
2222

2323
#define SPI_MAX_WORD_SIZE 32
2424
#define SPI_MAX_CS_SIZE 32
2525

2626
struct spi_litex_dev_config {
27-
uint32_t core_master_cs_addr;
28-
uint32_t core_master_phyconfig_addr;
29-
uint32_t core_master_rxtx_addr;
30-
uint32_t core_master_rxtx_size;
31-
uint32_t core_master_status_addr;
27+
uint32_t master_cs_addr;
28+
uint32_t master_phyconfig_addr;
29+
uint32_t master_rxtx_addr;
30+
uint32_t master_rxtx_size;
31+
uint32_t master_status_addr;
3232
uint32_t phy_clk_divisor_addr;
3333
bool phy_clk_divisor_exists;
3434
};
@@ -123,12 +123,12 @@ static void spiflash_len_mask_width_write(uint32_t len, uint32_t width, uint32_t
123123
uint32_t addr)
124124
{
125125
uint32_t tmp = len & BIT_MASK(8);
126-
uint32_t word = tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_LEN_OFFSET * 8);
126+
uint32_t word = tmp << (SPIFLASH_MASTER_PHYCONFIG_LEN_OFFSET * 8);
127127

128128
tmp = width & BIT_MASK(8);
129-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
129+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_WIDTH_OFFSET * 8);
130130
tmp = mask & BIT_MASK(8);
131-
word |= tmp << (SPIFLASH_CORE_MASTER_PHYCONFIG_MASK_OFFSET * 8);
131+
word |= tmp << (SPIFLASH_MASTER_PHYCONFIG_MASK_OFFSET * 8);
132132
litex_write32(word, addr);
133133
}
134134

@@ -145,22 +145,22 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
145145
uint8_t width = BIT(0); /* SPI Xfer width*/
146146
uint8_t mask = BIT(0); /* SPI Xfer mask*/
147147

148-
spiflash_len_mask_width_write(len * 8, width, mask, dev_config->core_master_phyconfig_addr);
148+
spiflash_len_mask_width_write(len * 8, width, mask, dev_config->master_phyconfig_addr);
149149

150-
litex_write32(BIT(config->slave), dev_config->core_master_cs_addr);
150+
litex_write32(BIT(config->slave), dev_config->master_cs_addr);
151151

152152
/* Flush RX buffer */
153-
while ((litex_read8(dev_config->core_master_status_addr) &
154-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
155-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
153+
while ((litex_read8(dev_config->master_status_addr) &
154+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
155+
rxd = litex_read32(dev_config->master_rxtx_addr);
156156
LOG_DBG("flushed rxd: 0x%x", rxd);
157157
}
158158

159159
do {
160-
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->core_master_rxtx_size);
160+
len = MIN(spi_context_max_continuous_chunk(ctx), dev_config->master_rxtx_size);
161161
if (len != old_len) {
162162
spiflash_len_mask_width_write(len * 8, width, mask,
163-
dev_config->core_master_phyconfig_addr);
163+
dev_config->master_phyconfig_addr);
164164
old_len = len;
165165
}
166166

@@ -170,22 +170,22 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
170170
txd = 0U;
171171
}
172172

173-
while (!(litex_read8(dev_config->core_master_status_addr) &
174-
BIT(SPIFLASH_CORE_MASTER_STATUS_TX_READY_OFFSET))) {
173+
while (!(litex_read8(dev_config->master_status_addr) &
174+
BIT(SPIFLASH_MASTER_STATUS_TX_READY_OFFSET))) {
175175
;
176176
}
177177

178178
LOG_DBG("txd: 0x%x", txd);
179-
litex_write32(txd, dev_config->core_master_rxtx_addr);
179+
litex_write32(txd, dev_config->master_rxtx_addr);
180180

181181
spi_context_update_tx(ctx, data->dfs, len / data->dfs);
182182

183-
while (!(litex_read8(dev_config->core_master_status_addr) &
184-
BIT(SPIFLASH_CORE_MASTER_STATUS_RX_READY_OFFSET))) {
183+
while (!(litex_read8(dev_config->master_status_addr) &
184+
BIT(SPIFLASH_MASTER_STATUS_RX_READY_OFFSET))) {
185185
;
186186
}
187187

188-
rxd = litex_read32(dev_config->core_master_rxtx_addr);
188+
rxd = litex_read32(dev_config->master_rxtx_addr);
189189
LOG_DBG("rxd: 0x%x", rxd);
190190

191191
if (spi_context_rx_buf_on(ctx)) {
@@ -196,7 +196,7 @@ static int spi_litex_xfer(const struct device *dev, const struct spi_config *con
196196

197197
} while (spi_context_tx_on(ctx) || spi_context_rx_on(ctx));
198198

199-
litex_write32(0, dev_config->core_master_cs_addr);
199+
litex_write32(0, dev_config->master_cs_addr);
200200

201201
spi_context_complete(ctx, dev, 0);
202202

@@ -260,11 +260,11 @@ static DEVICE_API(spi, spi_litex_api) = {
260260
SPI_CONTEXT_INIT_SYNC(spi_litex_data_##n, ctx), \
261261
}; \
262262
static struct spi_litex_dev_config spi_litex_cfg_##n = { \
263-
.core_master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_cs), \
264-
.core_master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_phyconfig), \
265-
.core_master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_rxtx), \
266-
.core_master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, core_master_rxtx), \
267-
.core_master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, core_master_status), \
263+
.master_cs_addr = DT_INST_REG_ADDR_BY_NAME(n, master_cs), \
264+
.master_phyconfig_addr = DT_INST_REG_ADDR_BY_NAME(n, master_phyconfig), \
265+
.master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, master_rxtx), \
266+
.master_rxtx_size = DT_INST_REG_SIZE_BY_NAME(n, master_rxtx), \
267+
.master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, master_status), \
268268
.phy_clk_divisor_exists = DT_INST_REG_HAS_NAME(n, phy_clk_divisor), \
269269
.phy_clk_divisor_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, phy_clk_divisor, 0) \
270270
\

‎dts/riscv/riscv32-litex-vexriscv.dtsi

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -102,11 +102,11 @@
102102
<0xe000c010 0x4>,
103103
<0xe000c800 0x4>,
104104
<0x60000000 0x1000000>;
105-
reg-names = "core_mmap_dummy_bits",
106-
"core_master_cs",
107-
"core_master_phyconfig",
108-
"core_master_rxtx",
109-
"core_master_status",
105+
reg-names = "mmap_dummy_bits",
106+
"master_cs",
107+
"master_phyconfig",
108+
"master_rxtx",
109+
"master_status",
110110
"phy_clk_divisor",
111111
"flash_mmap";
112112
#address-cells = <1>;

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