soc: renesas: rx: Initial support for RX261 SOC

This commit to initial support for RX261 SOC.

Signed-off-by: Hau Ho <hau.ho.xc@bp.renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>

Author: Hau Ho

soc/renesas/rx/rx261/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS ofsm.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/rx/linker.ld CACHE INTERNAL "")

soc/renesas/rx/rx261/Kconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RX261
+	select RX
+	select CPU_RXV3
+	select XIP
+	select CLOCK_CONTROL_RENESAS_RX_CGC if CLOCK_CONTROL
+	select HAS_RENESAS_RX_RDP
+	select CLOCK_CONTROL

soc/renesas/rx/rx261/Kconfig.defconfig

@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RX261
+
+DT_CMT_PATH := $(dt_nodelabel_path,cmt)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_CMT_PATH),clock-frequency)
+
+# SYS_CLOCK_TICKS_PER_SEC is set to 100 if PCLKB is 48MHz or less.
+# (PCLKB = SYS_CLOCK_HW_CYCLES_PER_SEC * 8)
+config SYS_CLOCK_TICKS_PER_SEC
+	default 100 if SYS_CLOCK_HW_CYCLES_PER_SEC <= 6000000
+	default 1000
+
+config INITIALIZATION_STACK_SIZE
+	int "Initialization stack size (in bytes)"
+	default 512
+
+endif # SOC_SERIES_RX261

soc/renesas/rx/rx261/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RX261
+	bool
+	select SOC_FAMILY_RENESAS_RX
+	help
+	  Renesas RX261 series
+
+config SOC_R5F52618BGFP
+	bool
+	select SOC_SERIES_RX261
+	help
+	  SOC_R5F52618BGFP
+
+config SOC_SERIES
+	default "rx261" if SOC_SERIES_RX261
+
+config SOC
+	default "r5f52618bgfp" if SOC_R5F52618BGFP

soc/renesas/rx/rx261/ofsm.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021 KT-Elektronik, Klaucke und Partner GmbH
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ *
+ * Option-Setting Memory for the RX. This region of memory (located in flash)
+ * determines the state of the MCU after reset and can not be changed on runtime
+ *
+ * All registers are set to 0xffffffff by default, which are "safe" settings.
+ * Please refer to the Renesas RX Group User's Manual before changing any of
+ * the values as some changes can be permanent or lock access to the device.
+ *
+ * Address range: 0xFE7F5D00 to 0xFE7F5D7F (128 Bytes)
+ */
+
+#define __OFS_MDE __attribute__((section(".ofs_mde")))
+
+/* Endian Select Register (MDE) at 0xFE7F5D00
+ *
+ * b2 to b0: endian select between (0 0 0) for big endian and (1 1 1) for little
+ * endian. Set this according to __BYTE_ORDER__ (cf. include\toolchain\gcc.h)
+ *
+ * b6-b4 (Bank Mode Select) indicate whether the flash is operated in
+ * Dual mode (0 0 0) or Linear mode (1 1 1).
+ *
+ * all other bits are reserved and have to be set to 1
+ */
+const unsigned long __OFS_MDE __MDEreg = 0xffffffff; /* little */
+
+struct st_ofs0 {
+	unsigned long res0: 1;
+	unsigned long IWDTSTRT: 1;
+	unsigned long IWDTTOPS: 2;
+	unsigned long IWDTCKS: 4;
+	unsigned long IWDTRPES: 2;
+	unsigned long IWDTRPSS: 2;
+	unsigned long IWDTRSTIRQS: 1;
+	unsigned long res1: 1;
+	unsigned long IWDTSLCSTP: 1;
+	unsigned long res2: 16;
+};
+
+const unsigned long __OFS_MDE __OFS0reg = 0xffffffff;
+
+/* Option Function Select Register 1 (OFS1) at 0xFE7F5D08 (Voltage detection and
+ * HOCO)
+ */
+const unsigned long __OFS_MDE __OFS1reg = 0xffffffff;

soc/renesas/rx/rx261/ofsm.ld

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.ofsm,,)
+{
+	__OFSM_START = .;
+	KEEP(*(.ofs_mde))
+	. = __OFSM_START + 0x8;
+	KEEP(*(.ofs1))
+	. = __OFSM_START + 0xC;
+	KEEP(*(.ofs0))
+	__OFSM_END = .;
+} GROUP_LINK_IN(OFSM) = 0xFF

soc/renesas/rx/rx261/soc.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief System/hardware module for RX SOC family
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <soc.h>
+
+#include "platform.h"
+#include "r_bsp_cpu.h"
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+void soc_early_init_hook(void)
+{
+#ifdef CONFIG_HAS_RENESAS_RX_RDP
+	bsp_ram_initialize();
+	bsp_interrupt_open();
+	bsp_register_protect_open();
+#if CONFIG_NONE_USED_PORT_INIT == 1
+	/*
+	 * This is the function that initializes the unused port.
+	 * Please see datails on this in the "Handling of Unused Pins" section of PORT chapter
+	 *  of RX MCU of User's manual.
+	 * And please MUST set "BSP_PACKAGE_PINS" definition to your device of pin type in
+	 * r_bsp_config.h Otherwise, the port may output without intention.
+	 */
+	bsp_non_existent_port_init();
+
+#endif /* CONFIG_NONE_USED_PORT_INIT */
+#endif /* CONFIG_HAS_RENESAS_RX_RDP */
+}

soc/renesas/rx/rx261/soc.h

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief SOC header file for Renesas RX SOC series
+ */
+
+#ifndef _SOC_H_
+#define _SOC_H_
+
+#include "reg_protection.h"
+#include <mcu_clocks.h>
+
+#endif /* _SOC_H_ */

soc/renesas/rx/soc.yml

@@ -7,3 +7,6 @@ family:
       - name: rx62n
         socs:
           - name: r5f562n8
+      - name: rx261
+        socs:
+          - name: r5f52618bgfp