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boards: aesc: Add ElemRV-N
ElemRV-N is an end-to-end open-source microcontroller. This patch adds basic support for the platform with any interfaces. They will be added later since drivers are missing completly. Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
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‎boards/aesc/elemrv/Kconfig.elemrv

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# Copyright (c) 2025 Aesc Silicon
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ELEMRV
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select SOC_ELEMRV_N

‎boards/aesc/elemrv/board.yml

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board:
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name: elemrv
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full_name: ElemRV-N
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vendor: aesc
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socs:
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- name: elemrv_n

‎boards/aesc/elemrv/doc/index.rst

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.. zephyr:board:: elemrv
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Overview
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********
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ElemRV-N is an end-to-end open-source RISC-V microcontroller designed using SpinalHDL.
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Version 0.2 of ElemRV-N was successfully fabricated using `IHP's Open PDK`_, a 130nm open semiconductor process, with support from `FMD-QNC`_.
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For more details, refer to the official `GitHub Project`_.
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.. note::
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The currently supported silicon version is ElemRV-N 0.2.
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Supported Features
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******************
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.. zephyr:board-supported-hw::
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System Clock
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============
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The system clock for the RISC-V core is set to 20 MHz. This value is specified in the ``cpu0`` devicetree node using the ``clock-frequency`` property.
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CPU
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===
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ElemRV-N integrates a VexRiscv RISC-V core featuring a 5-stage pipeline and the following ISA extensions:
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* M (Integer Multiply/Divide)
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* C (Compressed Instructions)
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It also includes the following general-purpose ``Z`` extensions:
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* Zicntr – Base Counter and Timer extensions
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* Zicsr – Control and Status Register operations
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* Zifencei – Instruction-fetch fence
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The complete ISA string for this CPU is: ``RV32IMC_Zicntr_Zicsr_Zifencei``
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Hart-Level Interrupt Controller (HLIC)
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======================================
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Each CPU core is equipped with a Hart-Level Interrupt Controller, configurable through Control and Status Registers (CSRs).
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Machine Timer
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=============
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A RISC-V compliant machine timer is enabled by default.
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Serial
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======
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The UART (Universal Asynchronous Receiver-Transmitter) interface is a configurable serial communication peripheral used for transmitting and receiving data.
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By default, ``uart0`` operates at a baud rate of ``115200``, which can be adjusted via the elemrv device tree.
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To evaluate the UART interface, build and run the following sample:
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.. zephyr-app-commands::
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:board: elemrv/elemrv_n
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:zephyr-app: samples/hello_world
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:goals: build
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.. _GitHub Project:
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https://github.com/aesc-silicon/elemrv
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.. _IHP's Open PDK:
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https://github.com/IHP-GmbH/IHP-Open-PDK
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.. _FMD-QNC:
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https://www.elektronikforschung.de/projekte/fmd-qnc

‎boards/aesc/elemrv/elemrv_elemrv_n.dts

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/*
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* Copyright (C) 2025 Aesc Silicon
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <aesc/elemrv-n.dtsi>
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/ {
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model = "ElemRV-N";
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compatible = "aesc,elemrv-n";
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &hyperbus;
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zephyr,flash = &flash;
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};
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soc {
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ocram: memory@80000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x80000000 DT_SIZE_K(1)>;
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};
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hyperbus: memory@90000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x90000000 DT_SIZE_K(32)>;
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};
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flash: flash@a0010000 {
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compatible = "soc-nv-flash";
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reg = <0xa0010000 DT_SIZE_K(32)>;
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};
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};
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};
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&uart0 {
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clock-frequency = <DT_FREQ_M(20)>;
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current-speed = <115200>;
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status = "okay";
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};
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&cpu0 {
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clock-frequency = <DT_FREQ_M(20)>;
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};

‎boards/aesc/elemrv/elemrv_elemrv_n.yaml

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identifier: elemrv/elemrv_n
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name: ElemRV-N
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type: mcu
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arch: riscv
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toolchain:
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- cross-compile
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- zephyr
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ram: 32
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flash: 32

‎boards/aesc/elemrv/elemrv_elemrv_n_defconfig

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# Copyright (c) 2025 Aesc Silicon
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# SPDX-License-Identifier: Apache-2.0
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# Serial Driver
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CONFIG_SERIAL=y
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# Enable Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y

‎boards/aesc/index.rst

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.. _boards-aesc:
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Aesc Silicon
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############
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.. toctree::
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:maxdepth: 1
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:glob:
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**/*

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