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Danh Doankartben
Danh Doan
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kartben
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boards: shields: add support shield rtk7eka6m3b00001bu
Add display shield rtk7eka6m3b00001bu support Signed-off-by: Danh Doan <danh.doan.ue@bp.renesas.com> Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
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‎boards/renesas/ek_ra8d1/Kconfig.defconfig

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@@ -12,7 +12,7 @@ endif # NETWORKING
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if DISPLAY
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if SHIELD_RTKMIPILCDB00000BE
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if SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU
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config MEMC
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default y
@@ -21,7 +21,7 @@ config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION
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default ".sdram"
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depends on RENESAS_RA_GLCDC
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endif # SHIELD_RTKMIPILCDB00000BE
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endif # SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU
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endif # DISPLAY
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‎boards/shields/rtk7eka6m3b00001bu/Kconfig.defconfig

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SHIELD_RTK7EKA6M3B00001BU
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if LVGL
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# Configure LVGL to use touchscreen with input API
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config INPUT
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default y
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# LVGL should allocate buffers equal to size of display
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config LV_Z_VDB_SIZE
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default 100
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# Enable double buffering
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config LV_Z_DOUBLE_VDB
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default y
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# Force full refresh. This prevents memory copy associated with partial
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# display refreshes, which is not necessary for the GLCDC driver
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config LV_Z_FULL_REFRESH
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default y
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config LV_Z_BITS_PER_PIXEL
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default 32
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# Use offloaded render thread
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config LV_Z_FLUSH_THREAD
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default y
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choice LV_COLOR_DEPTH
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default LV_COLOR_DEPTH_32
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endchoice
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endif # LVGL
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endif # SHIELD_RTK7EKA6M3B00001BU

‎boards/shields/rtk7eka6m3b00001bu/Kconfig.shield

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SHIELD_RTK7EKA6M3B00001BU
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def_bool $(shields_list_contains,rtk7eka6m3b00001bu)

‎boards/shields/rtk7eka6m3b00001bu/boards/ek_ra8d1.overlay

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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renesas_parallel_graphics_connector: parallel-graphics-connector {
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compatible = "renesas,ra-parallel-graphics-header";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <1 0 &ioport4 4 0>, /* DISP_BLEN */
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<2 0 &ioport5 11 0>, /* IIC_SDA */
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<3 0 &ioport5 10 0>, /* DISP_INT */
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<4 0 &ioport5 12 0>, /* IIC_SCL */
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<6 0 &ioporta 1 0>; /* DISP_RST */
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};
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};
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&port_irq3 {
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interrupts = <90 1>;
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status = "okay";
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};
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&pinctrl {
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glcdc_default: glcdc_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>, /* LCDC_TCON0 */
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<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>, /* LCDC_TCON1 */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>, /* LCDC_TCON2 */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>, /* LCDC_TCON3 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>, /* LCDC_DATA00 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>, /* LCDC_DATA01 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>, /* LCDC_DATA02 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>, /* LCDC_DATA03 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>, /* LCDC_DATA04 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>, /* LCDC_DATA05 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>, /* LCDC_DATA06 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>, /* LCDC_DATA07 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>, /* LCDC_DATA08 */
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<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>, /* LCDC_DATA09 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>, /* LCDC_DATA10 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>, /* LCDC_DATA11 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>, /* LCDC_DATA12 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>, /* LCDC_DATA13 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>, /* LCDC_DATA14 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>, /* LCDC_DATA15 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>, /* LCDC_DATA16 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>, /* LCDC_DATA17 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>, /* LCDC_DATA18 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>, /* LCDC_DATA19 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>, /* LCDC_DATA20 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>, /* LCDC_DATA21 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>, /* LCDC_DATA22 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>, /* LCDC_DATA23 */
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<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>, /* LCDC_CLK */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>; /* LCDC_EXTCLK */
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};
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};
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iic1_default: iic1_default {
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group1 {
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/* SCL1 SDA1 */
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psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
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<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
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drive-strength = "medium";
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};
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};
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};
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&zephyr_lcdif {
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pinctrl-0 = <&glcdc_default>;
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pinctrl-names = "default";
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output-pin-hsync = "TCON_PIN_1";
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output-pin-vsync = "TCON_PIN_0";
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output-pin-de = "TCON_PIN_2";
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};
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&iic1 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <DT_FREQ_K(100)>;
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pinctrl-0 = <&iic1_default>;
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pinctrl-names = "default";
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};

‎boards/shields/rtk7eka6m3b00001bu/doc/index.rst

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.. _rtk7eka6m3b00001bu:
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RTK7EKA6M3B00001BU Display
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##########################
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Overview
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********
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The Graphics Expansion Board includes a 4.3-inch 480x272 pixel TFT color LCD with a
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capacitive touch overlay.
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This display uses a 40-pin connector header.
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Pins Assignment of the Renesas RTK7EKA6M3B00001BU Display
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=========================================================
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+-----------------+--------------------------+
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| Connector Pin | Function |
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+=================+==========================+
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| 1 | Display backlight enable |
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+-----------------+--------------------------+
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| 2 | Touch ctrl I2C SDA |
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+-----------------+--------------------------+
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| 3 | External interrupt |
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+-----------------+--------------------------+
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| 4 | Touch ctrl I2C SCL |
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+-----------------+--------------------------+
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| 6 | Display reset |
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+-----------------+--------------------------+
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Hardware Requirements:
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**********************
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Supported Renesas RA boards: EK-RA8D1
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- 1 x RA Board
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- 1 x Micro USB cable
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Hardware Configuration:
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***********************
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The Graphics Expansion Port (J57) connects the EK-RA8D1 board to the Graphics Expansion Board
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supplied as part of the kit.
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Set the configuration switches (SW1) as below to avoid potential failures.
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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| OFF | OFF | OFF | OFF | OFF | ON | ON | OFF |
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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Programming
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***********
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Set ``--shield=rtk7eka6m3b00001bu`` when you invoke ``west build``. For
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example:
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.. zephyr-app-commands::
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:zephyr-app: tests/drivers/display/display_read_write
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:board: ek_ra8d1
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:shield: rtk7eka6m3b00001bu
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:goals: build

‎boards/shields/rtk7eka6m3b00001bu/rtk7eka6m3b00001bu.overlay

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/display/panel.h>
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/ {
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chosen {
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zephyr,display = &zephyr_lcdif;
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};
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lvgl_pointer {
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compatible = "zephyr,lvgl-pointer-input";
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input = <&ft5336_rtk7eka6m3b00001bu>;
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};
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};
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&iic1 {
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status = "okay";
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ft5336_rtk7eka6m3b00001bu: ft5336-rtk7eka6m3b00001bu@38 {
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compatible = "focaltech,ft5336";
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reg = <0x38>;
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int-gpios = <&renesas_parallel_graphics_connector 3 GPIO_ACTIVE_HIGH>;
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};
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};
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&zephyr_lcdif {
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status = "okay";
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width = <480>;
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height = <272>;
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input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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output-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
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display-timings {
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compatible = "zephyr,panel-timing";
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hsync-len = <1>;
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hback-porch = <40>;
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vsync-len = <1>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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hfront-porch = <4>;
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vfront-porch = <35>;
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};
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backlight-gpios = <&renesas_parallel_graphics_connector 1 GPIO_ACTIVE_HIGH>;
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};

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