soc: silabs: Add support for MG22 SoCs

loopj · loopj · commit 57294c79642a · 2025-07-07T15:01:59.000-07:00
Signed-off-by: James Smith &lt;james@loopj.com&gt;
diff --git a/drivers/entropy/Kconfig.gecko b/drivers/entropy/Kconfig.gecko
@@ -9,7 +9,7 @@ config ENTROPY_GECKO_TRNG
 	default y
 	depends on DT_HAS_SILABS_GECKO_TRNG_ENABLED
 	select ENTROPY_HAS_DRIVER
-	select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_EFR32BG22
+	select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_XG22
 	select CRYPTO_ACC_GECKO_TRNG if SOC_SERIES_EFR32BG27
 	help
 	  This option enables the true random number generator
diff --git a/dts/arm/silabs/xg22/efr32mg22.dtsi b/dts/arm/silabs/xg22/efr32mg22.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32xg22.dtsi>
+
+&radio {
+	bt_hci_silabs: bt_hci_silabs {
+		compatible = "silabs,bt-hci-efr32";
+		status = "disabled";
+	};
+};
diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512gn32.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512gn32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512GN32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};
diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512im32.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512im32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512IM32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};
diff --git a/dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi b/dts/arm/silabs/xg22/efr32mg22c224f512im40.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22c224f512im40", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22C224F512IM40 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};
diff --git a/dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi b/dts/arm/silabs/xg22/efr32mg22e224f512im32.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22e224f512im32", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22E224F512IM32 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};
diff --git a/dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi b/dts/arm/silabs/xg22/efr32mg22e224f512im40.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021 Sateesh Kotapati
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <silabs/xg22/efr32mg22.dtsi>
+#include <mem.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg22e224f512im40", "silabs,efr32mg22", "silabs,xg22",
+			     "silabs,efr32", "simple-bus";
+		model = "Silicon Labs EFR32MG22E224F512IM40 SoC";
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(32)>;
+};
diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h
@@ -11,7 +11,7 @@
 
 #if defined(CONFIG_SOC_SERIES_EFR32MG21)
 #include <zephyr/dt-bindings/clock/silabs/xg21-clock.h>
-#elif defined(CONFIG_SOC_SERIES_EFR32BG22)
+#elif defined(CONFIG_SOC_SERIES_XG22)
 #include <zephyr/dt-bindings/clock/silabs/xg22-clock.h>
 #elif defined(CONFIG_SOC_SERIES_EFR32ZG23)
 #include <zephyr/dt-bindings/clock/silabs/xg23-clock.h>
diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc
diff --git a/soc/silabs/silabs_s2/xg22/Kconfig b/soc/silabs/silabs_s2/xg22/Kconfig
@@ -1,4 +1,5 @@
 # Copyright (c) 2021 Sateesh Kotapati
+# Copyright (c) 2025 James Smith
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_EFR32BG22
@@ -19,5 +20,23 @@ config SOC_SERIES_EFR32BG22
 	select SOC_GECKO_SE
 	select HAS_PM
 
+config SOC_SERIES_EFR32MG22
+	select ARM
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_FPU
+	select HAS_SILABS_SISDK
+	select HAS_SWO
+	select SOC_GECKO_HAS_RADIO
+	select SOC_GECKO_GPIO
+	select SOC_GECKO_CMU
+	select SOC_GECKO_CORE
+	select SOC_GECKO_DEV_INIT
+	select SOC_GECKO_SE
+	select HAS_PM
+
 config SOC_GECKO_SDID
-	default 205 if SOC_SERIES_EFR32BG22
+	default 205 if SOC_SERIES_EFR32BG22 || SOC_SERIES_EFR32MG22
diff --git a/soc/silabs/silabs_s2/xg22/Kconfig.defconfig b/soc/silabs/silabs_s2/xg22/Kconfig.defconfig
@@ -1,7 +1,8 @@
 # Copyright (c) 2021 Sateesh Kotapati
+# Copyright (c) 2025 James Smith
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_EFR32BG22
+if SOC_SERIES_EFR32BG22 || SOC_SERIES_EFR32MG22
 
 config NUM_IRQS
 	# must be >= the highest interrupt number used
diff --git a/soc/silabs/silabs_s2/xg22/Kconfig.soc b/soc/silabs/silabs_s2/xg22/Kconfig.soc
@@ -0,0 +1,66 @@
+# Copyright (c) 2021 Sateesh Kotapati
+# Copyright (c) 2025 James Smith
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_XG22
+	bool
+	help
+	  Silicon Labs EFR32 22 Series SoC and modules
+
+config SOC_SERIES_EFR32BG22
+	bool
+	select SOC_FAMILY_SILABS_S2
+	select SOC_SERIES_XG22
+	help
+	  Silicon Labs EFR32BG22 (Blue Gecko) Series MCU
+
+config SOC_SERIES_EFR32MG22
+	bool
+	select SOC_FAMILY_SILABS_S2
+	select SOC_SERIES_XG22
+	help
+	  Silicon Labs EFR32MG22 (Mighty Gecko) Series MCU
+
+config SOC_PART_NUMBER_EFR32BG22C224F512IM40
+	bool
+	select SOC_SERIES_EFR32BG22
+
+config SOC_PART_NUMBER_EFR32MG22C224F512IM40
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_PART_NUMBER_EFR32MG22C224F512IM32
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_PART_NUMBER_EFR32MG22C224F512GN32
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_PART_NUMBER_EFR32MG22E224F512IM40
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_PART_NUMBER_EFR32MG22E224F512IM32
+	bool
+	select SOC_SERIES_EFR32MG22
+
+config SOC_SERIES
+	default "efr32bg22" if SOC_SERIES_EFR32BG22
+	default "efr32mg22" if SOC_SERIES_EFR32MG22
+
+config SOC
+	default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40
+	default "efr32mg22c224f512im40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40
+	default "efr32mg22c224f512im32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32
+	default "efr32mg22c224f512gn32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32
+	default "efr32mg22e224f512im40" if SOC_PART_NUMBER_EFR32MG22E224F512IM40
+	default "efr32mg22e224f512im32" if SOC_PART_NUMBER_EFR32MG22E224F512IM32
+
+config SOC_PART_NUMBER
+	default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40
+	default "EFR32MG22C224F512IM40" if SOC_PART_NUMBER_EFR32MG22C224F512IM40
+	default "EFR32MG22C224F512IM32" if SOC_PART_NUMBER_EFR32MG22C224F512IM32
+	default "EFR32MG22C224F512GN32" if SOC_PART_NUMBER_EFR32MG22C224F512GN32
+	default "EFR32MG22E224F512IM40" if SOC_PART_NUMBER_EFR32MG22E224F512IM40
+	default "EFR32MG22E224F512IM32" if SOC_PART_NUMBER_EFR32MG22E224F512IM32
diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml
@@ -47,6 +47,13 @@ family:
       - name: efr32bg22
         socs:
           - name: efr32bg22c224f512im40
+      - name: efr32mg22
+        socs:
+          - name: efr32mg22c224f512im40
+          - name: efr32mg22c224f512im32
+          - name: efr32mg22c224f512gn32
+          - name: efr32mg22e224f512im40
+          - name: efr32mg22e224f512im32
       - name: efr32mg24
         socs:
           - name: efr32mg24b220f1536im48
diff --git a/west.yml b/west.yml
@@ -235,7 +235,7 @@ manifest:
       groups:
         - hal
     - name: hal_silabs
-      revision: 190a144a16bed9a938a94543ed5bbc70c0552e0f
+      revision: pull/116/head
       path: modules/hal/silabs
       groups:
         - hal
