riscv: select ATOMIC_OPERATIONS based on RISCV_ISA_EXT_A

maass-hamburg · danieldegrasse · commit 514258aa23d4 · 2025-06-30T15:17:47.000-05:00
use RISCV_ISA_EXT_A to select ATOMIC_OPERATIONS_BUILTIN or
ATOMIC_OPERATIONS_C.

Signed-off-by: Fin Maaß &lt;f.maass@vogl-electronic.com&gt;
diff --git a/arch/Kconfig b/arch/Kconfig
@@ -107,6 +107,8 @@ config X86
 config RISCV
 	bool
 	select ARCH_IS_SET
+	select ATOMIC_OPERATIONS_C if !RISCV_ISA_EXT_A
+	select ATOMIC_OPERATIONS_BUILTIN if RISCV_ISA_EXT_A
 	select ARCH_SUPPORTS_COREDUMP
 	select ARCH_SUPPORTS_COREDUMP_PRIV_STACKS
 	select ARCH_SUPPORTS_ROM_START if !SOC_FAMILY_ESPRESSIF_ESP32
diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig
@@ -5,7 +5,6 @@ if BOARD_NEORV32_NEORV32_MINIMALBOOT
 
 config BOARD_NEORV32
 	select RISCV_ISA_RV32I
-	select ATOMIC_OPERATIONS_C
 
 endif # BOARD_NEORV32_NEORV32_MINIMALBOOT
 
@@ -14,6 +13,5 @@ if BOARD_NEORV32_NEORV32_UP5KDEMO
 config BOARD_NEORV32
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
-	select ATOMIC_OPERATIONS_C
 
 endif # BOARD_NEORV32_NEORV32_UP5KDEMO
diff --git a/soc/aesc/nitrogen/Kconfig b/soc/aesc/nitrogen/Kconfig
@@ -5,7 +5,6 @@ config SOC_SERIES_NITROGEN
 	select RISCV
 	select RISCV_PRIVILEGED
 	select INCLUDE_RESET_VECTOR
-	select ATOMIC_OPERATIONS_C
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_C
diff --git a/soc/bflb/bl60x/Kconfig b/soc/bflb/bl60x/Kconfig
@@ -3,7 +3,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_BL60X
-	select ATOMIC_OPERATIONS_C
 	select CLOCK_CONTROL
 	select CPU_HAS_FPU
 	select INCLUDE_RESET_VECTOR
diff --git a/soc/efinix/sapphire/Kconfig b/soc/efinix/sapphire/Kconfig
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_EFINIX_SAPPHIRE
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
diff --git a/soc/gd/gd32/gd32vf103/Kconfig b/soc/gd/gd32/gd32vf103/Kconfig
@@ -15,7 +15,6 @@ config SOC_SERIES_GD32VF103
 	select RISCV_HAS_CLIC
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select RISCV_SOC_CONTEXT_SAVE
-	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select GD32_HAS_AFIO_PINMUX
 	select GD32_HAS_IRC_40K
diff --git a/soc/intel/intel_niosv/niosv/Kconfig b/soc/intel/intel_niosv/niosv/Kconfig
@@ -5,7 +5,6 @@
 config SOC_SERIES_NIOSV
 	select RISCV
 	select RISCV_PRIVILEGED
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_A
diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig
@@ -13,7 +13,6 @@ if SOC_SERIES_IT8XXX2
 
 config SOC_IT8XXX2
 	select RISCV
-	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig
@@ -3,7 +3,6 @@
 
 config SOC_LITEX_VEXRISCV
 	select RISCV
-	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
diff --git a/soc/microchip/miv/miv/Kconfig b/soc/microchip/miv/miv/Kconfig
@@ -11,7 +11,6 @@ config SOC_SERIES_MIV
 	imply XIP
 
 config SOC_MIV
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig
@@ -13,7 +13,6 @@ config SOC_SERIES_POLARFIRE
 config SOC_POLARFIRE
 	select 64BIT
 	select SCHED_IPI_SUPPORTED
-	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
diff --git a/soc/nordic/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig
@@ -3,7 +3,6 @@
 
 config RISCV_CORE_NORDIC_VPR
 	bool
-	select ATOMIC_OPERATIONS_C
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_VECTORED_MODE
diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig b/soc/openhwgroup/cva6/cv32a6/Kconfig
@@ -5,7 +5,6 @@
 config SOC_CV32A6
 	select RISCV
 	select RISCV_PRIVILEGED
-	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_HAS_PLIC
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig b/soc/openhwgroup/cva6/cv64a6/Kconfig
@@ -7,7 +7,6 @@ config SOC_CV64A6
 	bool
 	select RISCV
 	select RISCV_PRIVILEGED
-	select ATOMIC_OPERATIONS_BUILTIN
 	select RISCV_HAS_PLIC
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH
diff --git a/soc/openisa/rv32m1/Kconfig b/soc/openisa/rv32m1/Kconfig
@@ -8,7 +8,6 @@ config SOC_OPENISA_RV32M1
 	select HAS_RV32M1_LPI2C
 	select HAS_RV32M1_LPSPI
 	select HAS_RV32M1_TPM
-	select ATOMIC_OPERATIONS_C
 	select VEGA_SDK_HAL
 	select RISCV_SOC_INTERRUPT_INIT
 	select CLOCK_CONTROL
diff --git a/soc/qemu/virt_riscv/Kconfig b/soc/qemu/virt_riscv/Kconfig
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_QEMU_VIRT_RISCV
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
diff --git a/soc/renode/riscv_virtual/Kconfig b/soc/renode/riscv_virtual/Kconfig
@@ -4,7 +4,6 @@
 config SOC_RISCV_VIRTUAL_RENODE
 	select RISCV
 	select RISCV_PRIVILEGED
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
diff --git a/soc/sensry/ganymed/sy1xx/Kconfig b/soc/sensry/ganymed/sy1xx/Kconfig
@@ -8,4 +8,3 @@ config SOC_SERIES_SY1XX
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_PRIVILEGED
-	select ATOMIC_OPERATIONS_C
diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig
@@ -18,7 +18,6 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 
-	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select SOC_EARLY_INIT_HOOK
 	imply XIP
diff --git a/soc/snps/nsim/arc_v/rmx/Kconfig b/soc/snps/nsim/arc_v/rmx/Kconfig
@@ -14,5 +14,4 @@ config SOC_SERIES_RMX
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select INCLUDE_RESET_VECTOR
-	select ATOMIC_OPERATIONS_BUILTIN
 	imply XIP
diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig
@@ -9,7 +9,6 @@ config SOC_SERIES_STARFIVE_JH71XX
 	imply XIP
 
 config SOC_JH7100
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
@@ -19,7 +18,6 @@ config SOC_JH7100
 	select RISCV_ISA_EXT_ZIFENCEI
 
 config SOC_JH7110
-	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig
@@ -14,7 +14,6 @@ config SOC_SERIES_TLSR951X
 	select RISCV_HAS_PLIC
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select HAS_TELINK_DRIVERS
-	select ATOMIC_OPERATIONS_BUILTIN
 	select CPU_HAS_FPU
 	select INCLUDE_RESET_VECTOR
 	imply XIP
diff --git a/soc/wch/ch32v/Kconfig b/soc/wch/ch32v/Kconfig
@@ -6,7 +6,6 @@ config SOC_FAMILY_CH32V
 	select RISCV
 	select BUILD_OUTPUT_HEX
 	select CH32V00X_SYSTICK
-	select ATOMIC_OPERATIONS_C
 	imply XIP
 
 if SOC_FAMILY_CH32V
