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Appana Durga Kedareswara raokartben
Appana Durga Kedareswara rao
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kartben
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soc: amd: Add support for AMD Versal Gen 2 RPU
Add support for the RPU, real-time processing unit on Versal Gen 2 SoC. It is based on Cortext-R52 processor. The patch contains initial wiring and configuration for generic board with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global timer and UART. versal2.dtsi contains common peripherals integrated into Versal Gen 2 SoC, and versal2_r52.dtsi has peripherals which are private to Cortex-R52 processor. Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
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‎dts/arm/xilinx/versal2_r52.dtsi

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/*
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* Copyright (c) 2025, Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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#include <amd/versal2.dtsi>
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/ {
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model = "Versal Gen 2 RPU";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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status = "okay";
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};
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};
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&soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@e2000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0xe2000000 0x10000>, <0xe2100000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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};

‎dts/vendor/amd/versal2.dtsi

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/*
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* Copyright (c) 2025, Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc: soc {
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ocm: memory@bbf00000 {
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compatible = "zephyr,memory-region";
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reg = <0xbbf00000 DT_SIZE_M(1)>;
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status = "disabled";
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zephyr,memory-region = "OCM";
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};
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uart0: uart@f1920000 {
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compatible = "arm,sbsa-uart";
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reg = <0xf1920000 0x4c>;
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status = "disabled";
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interrupt-names = "irq_0";
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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uart1: uart@f1930000 {
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compatible = "arm,sbsa-uart";
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reg = <0xf1930000 0x1000>;
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status = "disabled";
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interrupt-names = "irq_1";
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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};
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};

‎soc/xlnx/versal2/CMakeLists.txt

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(
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CONFIG_ARM_MPU
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arm_mpu_regions.c
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)
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zephyr_include_directories(.)
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if(CONFIG_SOC_AMD_VERSAL2_RPU)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
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endif()

‎soc/xlnx/versal2/Kconfig

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_AMD_VERSAL2_RPU
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select ARM
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select ARM_ARCH_TIMER
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select CPU_CORTEX_R52
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select SOC_EARLY_INIT_HOOK
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select CPU_HAS_DCLS
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select GIC_SINGLE_SECURITY_STATE
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select CPU_HAS_ARM_MPU
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select ARM_MPU

‎soc/xlnx/versal2/Kconfig.defconfig

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_AMD_VERSAL2
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if SOC_AMD_VERSAL2_RPU
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config NUM_IRQS
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# must be >= the highest interrupt number used
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# - include the UART interrupts
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default 256
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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endif # SOC_AMD_VERSAL2_RPU
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endif # SOC_VERSAL2_AMD

‎soc/xlnx/versal2/Kconfig.soc

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#
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# Copyright (c) 2025 Advanced Micro Devices, Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_AMD_VERSAL2
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bool
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config SOC_AMD_VERSAL2_RPU
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bool
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select SOC_AMD_VERSAL2
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help
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AMD Versal Gen 2 RPU
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config SOC_FAMILY
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default "amd_versal2" if SOC_AMD_VERSAL2
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config SOC
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default "amd_versal2_rpu" if SOC_AMD_VERSAL2_RPU

‎soc/xlnx/versal2/arm_mpu_regions.c

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/*
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* Copyright (c) 2025 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/arch/arm/mpu/arm_mpu.h>
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#define DEVICE_REGION_START 0xE2000000U
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#define DEVICE_REGION_END 0xF8000000U
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("vector",
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(uintptr_t)_vector_start,
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REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)),
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MPU_REGION_ENTRY("SRAM_TEXT",
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(uintptr_t)__text_region_start,
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REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)),
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MPU_REGION_ENTRY("SRAM_RODATA",
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(uintptr_t)__rodata_region_start,
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REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
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MPU_REGION_ENTRY("SRAM_DATA",
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(uintptr_t)__rom_region_end,
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REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
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MPU_REGION_ENTRY("DEVICE",
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DEVICE_REGION_START,
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REGION_DEVICE_ATTR(DEVICE_REGION_END)),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};

‎soc/xlnx/versal2/soc.c

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/*
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* Copyright (c) 2025 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/cache.h>
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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void soc_early_init_hook(void)
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{
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if (IS_ENABLED(CONFIG_ICACHE)) {
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if (!(__get_SCTLR() & SCTLR_I_Msk)) {
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L1C_InvalidateICacheAll();
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__set_SCTLR(__get_SCTLR() | SCTLR_I_Msk);
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barrier_isync_fence_full();
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}
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}
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if (IS_ENABLED(CONFIG_DCACHE)) {
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if (!(__get_SCTLR() & SCTLR_C_Msk)) {
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L1C_InvalidateDCacheAll();
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__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
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barrier_dsync_fence_full();
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}
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}
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}

‎soc/xlnx/versal2/soc.h

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/*
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* Copyright (c) 2025 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_XLNX_VERSAL2_SOC_H_
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#define _SOC_XLNX_VERSAL2_SOC_H_
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/* Define CMSIS configurations */
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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#endif /* _SOC_XLNX_VERSAL2_SOC_H_ */

‎soc/xlnx/versal2/soc.yml

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family:
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- name: amd_versal2
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socs:
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- name: amd_versal2_rpu

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