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str4t0mMaureenHelm
str4t0m
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MaureenHelm
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drivers: adc: stm32: add support for stm32g0 series
Adds support for ADC on G0 series. Simple implementation: sequencer not fully configurable, and only one common sampling time. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
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+64
-12
lines changed

2 files changed

+64
-12
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‎drivers/adc/adc_stm32.c

Lines changed: 53 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ LOG_MODULE_REGISTER(adc_stm32);
2929
#include <pinmux/stm32/pinmux_stm32.h>
3030

3131
#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
32+
!defined(CONFIG_SOC_SERIES_STM32G0X) && \
3233
!defined(CONFIG_SOC_SERIES_STM32L0X)
3334
#define RANK(n) LL_ADC_REG_RANK_##n
3435
static const uint32_t table_rank[] = {
@@ -148,7 +149,8 @@ static const uint32_t table_samp_time[] = {
148149
SMP_TIME(239, S_5),
149150
};
150151
#endif /* ADC5_V1_1 */
151-
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
152+
#elif defined(CONFIG_SOC_SERIES_STM32L0X) || \
153+
defined(CONFIG_SOC_SERIES_STM32G0X)
152154
static const uint16_t acq_time_tbl[8] = {2, 4, 8, 13, 20, 40, 80, 161};
153155
static const uint32_t table_samp_time[] = {
154156
SMP_TIME(1, _5),
@@ -211,7 +213,9 @@ struct adc_stm32_data {
211213

212214
uint8_t resolution;
213215
uint8_t channel_count;
214-
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
216+
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
217+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
218+
defined(CONFIG_SOC_SERIES_STM32L0X)
215219
int8_t acq_time_index;
216220
#endif
217221
};
@@ -256,6 +260,7 @@ static void adc_stm32_start_conversion(const struct device *dev)
256260
defined(CONFIG_SOC_SERIES_STM32L0X) || \
257261
defined(CONFIG_SOC_SERIES_STM32L4X) || \
258262
defined(CONFIG_SOC_SERIES_STM32WBX) || \
263+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
259264
defined(CONFIG_SOC_SERIES_STM32G4X) || \
260265
defined(CONFIG_SOC_SERIES_STM32H7X)
261266
LL_ADC_REG_StartConversion(adc);
@@ -332,6 +337,11 @@ static int start_read(const struct device *dev,
332337
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
333338
defined(CONFIG_SOC_SERIES_STM32L0X)
334339
LL_ADC_REG_SetSequencerChannels(adc, channel);
340+
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
341+
/* STM32G0 in "not fully configurable" sequencer mode */
342+
LL_ADC_REG_SetSequencerChannels(adc, channel);
343+
while (LL_ADC_IsActiveFlag_CCRDY(adc) == 0) {
344+
}
335345
#else
336346
LL_ADC_REG_SetSequencerRanks(adc, table_rank[0], channel);
337347
LL_ADC_REG_SetSequencerLength(adc, table_seq_len[0]);
@@ -343,7 +353,21 @@ static int start_read(const struct device *dev,
343353
return err;
344354
}
345355

346-
#if !defined(CONFIG_SOC_SERIES_STM32F1X)
356+
#if defined(CONFIG_SOC_SERIES_STM32G0X)
357+
/*
358+
* Errata: Writing ADC_CFGR1 register while ADEN bit is set
359+
* resets RES[1:0] bitfield. We need to disable and enable adc.
360+
*/
361+
if (LL_ADC_IsEnabled(adc) == 1UL) {
362+
LL_ADC_Disable(adc);
363+
}
364+
while (LL_ADC_IsEnabled(adc) == 1UL) {
365+
}
366+
LL_ADC_SetResolution(adc, resolution);
367+
LL_ADC_Enable(adc);
368+
while (LL_ADC_IsActiveFlag_ADRDY(adc) != 1UL) {
369+
}
370+
#elif !defined(CONFIG_SOC_SERIES_STM32F1X)
347371
LL_ADC_SetResolution(adc, resolution);
348372
#endif
349373

@@ -352,6 +376,7 @@ static int start_read(const struct device *dev,
352376
defined(CONFIG_SOC_SERIES_STM32L0X) || \
353377
defined(CONFIG_SOC_SERIES_STM32L4X) || \
354378
defined(CONFIG_SOC_SERIES_STM32WBX) || \
379+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
355380
defined(CONFIG_SOC_SERIES_STM32G4X) || \
356381
defined(CONFIG_SOC_SERIES_STM32H7X)
357382
LL_ADC_EnableIT_EOC(adc);
@@ -457,6 +482,9 @@ static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
457482
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
458483
LL_ADC_SetSamplingTimeCommonChannels(adc,
459484
table_samp_time[acq_time_index]);
485+
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
486+
LL_ADC_SetSamplingTimeCommonChannels(adc, LL_ADC_SAMPLINGTIME_COMMON_1,
487+
table_samp_time[acq_time_index]);
460488
#else
461489
LL_ADC_SetChannelSamplingTime(adc,
462490
__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
@@ -467,7 +495,9 @@ static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
467495
static int adc_stm32_channel_setup(const struct device *dev,
468496
const struct adc_channel_cfg *channel_cfg)
469497
{
470-
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
498+
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
499+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
500+
defined(CONFIG_SOC_SERIES_STM32L0X)
471501
struct adc_stm32_data *data = dev->data;
472502
#endif
473503
int acq_time_index;
@@ -482,7 +512,9 @@ static int adc_stm32_channel_setup(const struct device *dev,
482512
if (acq_time_index < 0) {
483513
return acq_time_index;
484514
}
485-
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
515+
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
516+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
517+
defined(CONFIG_SOC_SERIES_STM32L0X)
486518
if (data->acq_time_index == -1) {
487519
data->acq_time_index = acq_time_index;
488520
} else {
@@ -533,6 +565,7 @@ static void adc_stm32_calib(const struct device *dev)
533565
defined(CONFIG_SOC_SERIES_STM32G4X)
534566
LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
535567
#elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
568+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
536569
defined(CONFIG_SOC_SERIES_STM32L0X)
537570
LL_ADC_StartCalibration(adc);
538571
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
@@ -555,12 +588,15 @@ static int adc_stm32_init(const struct device *dev)
555588
LOG_DBG("Initializing....");
556589

557590
data->dev = dev;
558-
#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
591+
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
592+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
593+
defined(CONFIG_SOC_SERIES_STM32L0X)
559594
/*
560595
* All conversion time for all channels on one ADC instance for F0 and
561-
* L0 series chips has to be the same. This additional variable is for
562-
* checking if the conversion time selection of all channels on one ADC
563-
* instance is the same.
596+
* L0 series chips has to be the same. For STM32G0 currently only one
597+
* of the two available common channel conversion times is used.
598+
* This additional variable is for checking if the conversion time
599+
* selection of all channels on one ADC instance is the same.
564600
*/
565601
data->acq_time_index = -1;
566602
#endif
@@ -591,12 +627,13 @@ static int adc_stm32_init(const struct device *dev)
591627
LL_ADC_DisableDeepPowerDown(adc);
592628
#endif
593629
/*
594-
* F3, L4, WB and G4 ADC modules need some time to be stabilized before
595-
* performing any enable or calibration actions.
630+
* F3, L4, WB, G0 and G4 ADC modules need some time
631+
* to be stabilized before performing any enable or calibration actions.
596632
*/
597633
#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
598634
defined(CONFIG_SOC_SERIES_STM32L4X) || \
599635
defined(CONFIG_SOC_SERIES_STM32WBX) || \
636+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
600637
defined(CONFIG_SOC_SERIES_STM32G4X) || \
601638
defined(CONFIG_SOC_SERIES_STM32H7X)
602639
LL_ADC_EnableInternalRegulator(adc);
@@ -609,6 +646,7 @@ static int adc_stm32_init(const struct device *dev)
609646
#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
610647
defined(CONFIG_SOC_SERIES_STM32L4X) || \
611648
defined(CONFIG_SOC_SERIES_STM32WBX) || \
649+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
612650
defined(CONFIG_SOC_SERIES_STM32G4X) || \
613651
defined(CONFIG_SOC_SERIES_STM32H7X)
614652
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
@@ -634,6 +672,7 @@ static int adc_stm32_init(const struct device *dev)
634672
defined(CONFIG_SOC_SERIES_STM32L0X) || \
635673
defined(CONFIG_SOC_SERIES_STM32L4X) || \
636674
defined(CONFIG_SOC_SERIES_STM32WBX) || \
675+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
637676
defined(CONFIG_SOC_SERIES_STM32G4X) || \
638677
defined(CONFIG_SOC_SERIES_STM32H7X)
639678
if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
@@ -653,6 +692,7 @@ static int adc_stm32_init(const struct device *dev)
653692
defined(CONFIG_SOC_SERIES_STM32L0X) || \
654693
defined(CONFIG_SOC_SERIES_STM32L4X) || \
655694
defined(CONFIG_SOC_SERIES_STM32WBX) || \
695+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
656696
defined(CONFIG_SOC_SERIES_STM32G4X) || \
657697
defined(CONFIG_SOC_SERIES_STM32H7X)
658698
/*
@@ -677,10 +717,11 @@ static int adc_stm32_init(const struct device *dev)
677717

678718
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
679719
defined(CONFIG_SOC_SERIES_STM32WBX) || \
720+
defined(CONFIG_SOC_SERIES_STM32G0X) || \
680721
defined(CONFIG_SOC_SERIES_STM32G4X) || \
681722
defined(CONFIG_SOC_SERIES_STM32H7X)
682723
/*
683-
* Enabling ADC modules in L4, WB and G4 series may fail if they are
724+
* Enabling ADC modules in L4, WB, G0 and G4 series may fail if they are
684725
* still not stabilized, this will wait for a short time to ensure ADC
685726
* modules are properly enabled.
686727
*/

‎dts/arm/st/g0/stm32g0.dtsi

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,17 @@
230230
status = "disabled";
231231
label = "SPI_2";
232232
};
233+
234+
adc1: adc@40012400 {
235+
compatible = "st,stm32-adc";
236+
reg = <0x40012400 0x400>;
237+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
238+
interrupts = <12 0>;
239+
interrupt-names = "combined";
240+
status = "disabled";
241+
label = "ADC_1";
242+
#io-channel-cells = <1>;
243+
};
233244
};
234245
};
235246

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