drivers: timer: nrf_rtc_timer: Allow use of custom bit width

Allowed use of counter bit width lower than hardware 24.
In that case, PPI connection is estabilished to trigger
clear tast once maximum value is reached.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>

Author: mstasiaknordic

drivers/timer/Kconfig.nrf_rtc

@@ -42,4 +42,12 @@ config NRF_RTC_TIMER_TRIGGER_OVERFLOW
 	  When enabled, a function can be used to trigger RTC overflow and
 	  effectively shift time into the future.
 
+config NRF_RTC_COUNTER_BIT_WIDTH
+	int "Bit width of RTC counter"
+	default 24
+	help
+	  Use custom bit width of RTC counter. If bit width other than 24 bits
+	  is used then one RTC channel will be reserved to control wrapping via
+	  PPI connections.
+
 endif # NRF_RTC_TIMER

drivers/timer/nrf_rtc_timer.c

@@ -17,11 +17,21 @@
 #include <haly/nrfy_rtc.h>
 #include <zephyr/irq.h>
 
+/* Ensure that selected counter bit width is withing its maximum hardware width. */
+BUILD_ASSERT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH <= 24, "Counter bit width exceeds maximum width.");
+
+#if (CONFIG_NRF_RTC_COUNTER_BIT_WIDTH < 24)
+#define CUSTOM_COUNTER_BIT_WIDTH 1
+#include "nrfx_ppi.h"
+#else
+#define CUSTOM_COUNTER_BIT_WIDTH 0
+#endif
+
 #define RTC_PRETICK (IS_ENABLED(CONFIG_SOC_NRF53_RTC_PRETICK) && \
 		     IS_ENABLED(CONFIG_SOC_NRF5340_CPUNET))
 
 #define EXT_CHAN_COUNT CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT
-#define CHAN_COUNT (EXT_CHAN_COUNT + 1)
+#define CHAN_COUNT (EXT_CHAN_COUNT + 1 + CUSTOM_COUNTER_BIT_WIDTH)
 
 #define RTC NRF_RTC1
 #define RTC_IRQn NRFX_IRQ_NUMBER_GET(RTC)
@@ -33,7 +43,7 @@ BUILD_ASSERT(CHAN_COUNT <= CHAN_COUNT_MAX, "Not enough compare channels");
 BUILD_ASSERT(DT_NODE_HAS_STATUS(DT_NODELABEL(RTC_LABEL), disabled),
 	     "Counter for RTC1 must be disabled");
 
-#define COUNTER_BIT_WIDTH 24U
+#define COUNTER_BIT_WIDTH CONFIG_NRF_RTC_COUNTER_BIT_WIDTH
 #define COUNTER_SPAN BIT(COUNTER_BIT_WIDTH)
 #define COUNTER_MAX (COUNTER_SPAN - 1U)
 #define COUNTER_HALF_SPAN (COUNTER_SPAN / 2U)
@@ -560,8 +570,13 @@ void rtc_nrf_isr(const void *arg)
 		rtc_pretick_rtc1_isr_hook();
 	}
 
-	if (nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
-	    nrfy_rtc_events_process(RTC, NRF_RTC_INT_OVERFLOW_MASK)) {
+	if ((nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_OVERFLOW_MASK) &&
+	    nrfy_rtc_events_process(RTC, NRF_RTC_INT_OVERFLOW_MASK)) ||
+#if CUSTOM_COUNTER_BIT_WIDTH
+	    (nrfy_rtc_int_enable_check(RTC, NRF_RTC_INT_COMPARE1_MASK) &&
+	    nrfy_rtc_events_process(RTC, NRF_RTC_INT_COMPARE1_MASK)) ||
+#endif
+		0) {
 		overflow_cnt++;
 	}
 
@@ -697,7 +712,9 @@ uint32_t sys_clock_cycle_get_32(void)
 static void int_event_disable_rtc(void)
 {
 	uint32_t mask = NRF_RTC_INT_TICK_MASK     |
+#if !CUSTOM_COUNTER_BIT_WIDTH
 			NRF_RTC_INT_OVERFLOW_MASK |
+#endif
 			NRF_RTC_INT_COMPARE0_MASK |
 			NRF_RTC_INT_COMPARE1_MASK |
 			NRF_RTC_INT_COMPARE2_MASK |
@@ -729,7 +746,9 @@ static int sys_clock_driver_init(void)
 		nrfy_rtc_int_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
 	}
 
+#if !CUSTOM_COUNTER_BIT_WIDTH
 	nrfy_rtc_int_enable(RTC, NRF_RTC_INT_OVERFLOW_MASK);
+#endif
 
 	NVIC_ClearPendingIRQ(RTC_IRQn);
 
@@ -742,7 +761,7 @@ static int sys_clock_driver_init(void)
 
 	int_mask = BIT_MASK(CHAN_COUNT);
 	if (CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT) {
-		alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << 1;
+		alloc_mask = BIT_MASK(EXT_CHAN_COUNT) << (1 + CUSTOM_COUNTER_BIT_WIDTH);
 	}
 
 	uint32_t initial_timeout = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
@@ -761,6 +780,28 @@ static int sys_clock_driver_init(void)
 	z_nrf_clock_control_lf_on(mode);
 #endif
 
+#if CUSTOM_COUNTER_BIT_WIDTH
+	/* Use channel 1 for wrapping. */
+	uint8_t chan = 1;
+	nrf_rtc_event_t evt = NRF_RTC_CHANNEL_EVENT_ADDR(chan);
+	nrfx_err_t result;
+	nrf_ppi_channel_t ch;
+
+	nrfy_rtc_event_enable(RTC, NRF_RTC_CHANNEL_INT_MASK(chan));
+	nrfy_rtc_cc_set(RTC, chan, COUNTER_MAX);
+	uint32_t evt_addr;
+	uint32_t task_addr;
+
+	evt_addr = nrfy_rtc_event_address_get(RTC, evt);
+	task_addr = nrfy_rtc_task_address_get(RTC, NRF_RTC_TASK_CLEAR);
+
+	result = nrfx_ppi_channel_alloc(&ch);
+	if (result != NRFX_SUCCESS) {
+		return -ENODEV;
+	}
+	(void)nrfx_ppi_channel_assign(ch, evt_addr, task_addr);
+	(void)nrfx_ppi_channel_enable(ch);
+#endif
 	return 0;
 }
 

include/zephyr/drivers/timer/nrf_rtc_timer.h

@@ -15,7 +15,7 @@ extern "C" {
 
 /** @brief Maximum allowed time span that is considered to be in the future.
  */
-#define NRF_RTC_TIMER_MAX_SCHEDULE_SPAN BIT(23)
+#define NRF_RTC_TIMER_MAX_SCHEDULE_SPAN BIT(CONFIG_NRF_RTC_COUNTER_BIT_WIDTH - 1)
 
 /** @brief RTC timer compare event handler.
  *

tests/drivers/timer/nrf_rtc_timer/src/main.c

@@ -361,6 +361,11 @@ static void overflow_sched_handler(int32_t id, uint64_t expire_time,
  */
 ZTEST(nrf_rtc_timer, test_overflow)
 {
+	/* For bit width lower than default 24, overflow injection is not possible. */
+	if (CONFIG_NRF_RTC_COUNTER_BIT_WIDTH < 24)
+	{
+		ztest_test_skip();
+	}
 	PRINT("RTC ticks before overflow injection: %u\r\n",
 	      (uint32_t)z_nrf_rtc_timer_read());
 

tests/drivers/timer/nrf_rtc_timer/testcase.yaml

@@ -23,3 +23,15 @@ tests:
       - nrf5340bsim/nrf5340/cpunet
     integration_platforms:
       - nrf52dk/nrf52832
+
+  drivers.timer.nrf_rtc_timer_16_bits:
+    tags:
+      - drivers
+      - timer
+    platform_allow:
+      - nrf52dk/nrf52832
+    integration_platforms:
+      - nrf52dk/nrf52832
+    extra_configs:
+      - CONFIG_ZERO_LATENCY_IRQS=y
+      - CONFIG_NRF_RTC_COUNTER_BIT_WIDTH=16