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drivers: gpio: add gpio support for sy1xx
Add gpio support for sensry soc sy1xx. Signed-off-by: Sven Ginka <s.ginka@sensry.de>
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‎drivers/gpio/CMakeLists.txt

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@@ -99,6 +99,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_STELLARIS gpio_stellaris.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_STM32 gpio_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_STMPE1600 gpio_stmpe1600.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_SX1509B gpio_sx1509b.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_SY1XX gpio_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TCA6424A gpio_tca6424a.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TEST gpio_test.c)

‎drivers/gpio/Kconfig

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@@ -183,6 +183,7 @@ source "drivers/gpio/Kconfig.stellaris"
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source "drivers/gpio/Kconfig.stm32"
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source "drivers/gpio/Kconfig.stmpe1600"
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source "drivers/gpio/Kconfig.sx1509b"
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source "drivers/gpio/Kconfig.sy1xx"
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source "drivers/gpio/Kconfig.tca6424a"
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source "drivers/gpio/Kconfig.test"
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source "drivers/gpio/Kconfig.tle9104"

‎drivers/gpio/Kconfig.sy1xx

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# Copyright (c) 2024 sensry.io
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_SY1XX
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bool "SY1XX GPIO driver"
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default y
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depends on DT_HAS_SENSRY_SY1XX_GPIO_ENABLED
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help
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Enable the SY1XX GPIO driver.

‎drivers/gpio/gpio_sy1xx.c

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/*
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* Copyright (c) 2024 sensry.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sensry_sy1xx_gpio
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(sy1xx_gpio, CONFIG_GPIO_LOG_LEVEL);
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <pinctrl_soc.h>
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#include <zephyr/drivers/pinctrl.h>
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#define SY1XX_GPIO_GET_OFFS 0x00
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#define SY1XX_GPIO_SET_OFFS 0x1c
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#define SY1XX_GPIO_CLR_OFFS 0x20
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struct sy1xx_gpio_config {
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/* Base address for GPIO port*/
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uint32_t port_base_addr;
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/* configuration base address for the pad config */
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uint32_t pad_cfg_offs;
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/* mask of pins which are allowed to modify by the gpio driver */
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uint32_t pin_mask;
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};
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/* Function prototypes for the GPIO API */
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static int sy1xx_gpio_driver_configure(const struct device *dev, gpio_pin_t pin,
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gpio_flags_t flags);
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static int sy1xx_gpio_driver_port_get_raw(const struct device *dev, gpio_port_value_t *value);
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static int sy1xx_gpio_driver_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value);
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static int sy1xx_gpio_driver_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins);
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static int sy1xx_gpio_driver_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins);
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static int sy1xx_gpio_driver_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins);
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static int sy1xx_gpio_driver_init(const struct device *dev)
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{
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return 0;
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}
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int sy1xx_gpio_driver_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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if (((BIT(pin)) & cfg->pin_mask) == 0) {
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return -EINVAL;
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}
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/* initialize the pinctrl config for the given gpio pin */
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pinctrl_soc_pin_t pcfg = {
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.addr = cfg->pad_cfg_offs + ROUND_DOWN(pin, 4),
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.iro = (pin % 4) * 8,
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.cfg = 0,
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};
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/* translate gpio flags into pinctrl config */
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if (flags & GPIO_INPUT) {
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if (flags & GPIO_PULL_UP) {
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pcfg.cfg |= BIT(SY1XX_PAD_PULL_UP_OFFS);
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}
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if (flags & GPIO_PULL_DOWN) {
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pcfg.cfg |= BIT(SY1XX_PAD_PULL_DOWN_OFFS);
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}
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} else if (flags & GPIO_OUTPUT) {
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pcfg.cfg |= BIT(SY1XX_PAD_DIR_OFFS);
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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sy1xx_gpio_driver_port_set_masked_raw(dev, BIT(pin), 0);
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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sy1xx_gpio_driver_port_set_masked_raw(dev, BIT(pin), BIT(pin));
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}
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} else if (flags == GPIO_DISCONNECTED) {
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pcfg.cfg |= BIT(SY1XX_PAD_TRISTATE_OFFS);
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} else {
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LOG_ERR("%s: unsupported pinctrl mode for pin: %u", dev->name, pin);
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return -ENOTSUP;
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}
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/* PAD config */
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int32_t ret = pinctrl_configure_pins(&pcfg, 1, PINCTRL_STATE_DEFAULT);
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if (ret != 0) {
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LOG_ERR("%s: failed to apply pinctrl for pin: %u", dev->name, pin);
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return -EINVAL;
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}
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return 0;
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}
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int sy1xx_gpio_driver_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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*value = sys_read32(cfg->port_base_addr | SY1XX_GPIO_GET_OFFS);
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return 0;
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}
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int sy1xx_gpio_driver_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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uint32_t set_mask = (mask & value) & (cfg->pin_mask);
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uint32_t clr_mask = (mask & (~value)) & (cfg->pin_mask);
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sy1xx_gpio_driver_port_set_bits_raw(dev, set_mask);
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sy1xx_gpio_driver_port_clear_bits_raw(dev, clr_mask);
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return 0;
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}
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int sy1xx_gpio_driver_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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/* affects only pins that are set to logical '1' */
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sys_write32((uint32_t)pins, cfg->port_base_addr | SY1XX_GPIO_SET_OFFS);
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return 0;
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}
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int sy1xx_gpio_driver_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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/* affects only pins that are set to logical '1' */
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sys_write32((uint32_t)pins, cfg->port_base_addr | SY1XX_GPIO_CLR_OFFS);
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return 0;
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}
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int sy1xx_gpio_driver_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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const struct sy1xx_gpio_config *const cfg = dev->config;
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uint32_t current = sys_read32(cfg->port_base_addr | SY1XX_GPIO_GET_OFFS);
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sy1xx_gpio_driver_port_set_masked_raw(dev, pins, ~current);
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return 0;
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}
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/* Define the GPIO API structure */
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static const struct gpio_driver_api sy1xx_gpio_driver_api = {
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.pin_configure = sy1xx_gpio_driver_configure,
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.port_get_raw = sy1xx_gpio_driver_port_get_raw,
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.port_set_masked_raw = sy1xx_gpio_driver_port_set_masked_raw,
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.port_set_bits_raw = sy1xx_gpio_driver_port_set_bits_raw,
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.port_clear_bits_raw = sy1xx_gpio_driver_port_clear_bits_raw,
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.port_toggle_bits = sy1xx_gpio_driver_port_toggle_bits,
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};
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#define SY1XX_GPIO_INIT(n) \
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\
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static const struct sy1xx_gpio_config sy1xx_gpio_##n##_config = { \
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.port_base_addr = (uint32_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
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.pad_cfg_offs = (uint32_t)DT_INST_PROP(n, pad_cfg), \
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.pin_mask = (uint32_t)GPIO_PORT_PIN_MASK_FROM_DT_INST(n)}; \
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\
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DEVICE_DT_INST_DEFINE(n, sy1xx_gpio_driver_init, NULL, NULL, &sy1xx_gpio_##n##_config, \
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &sy1xx_gpio_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(SY1XX_GPIO_INIT)

‎dts/bindings/gpio/sensry,sy1xx-gpio.yaml

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# Copyright (c) 2024 sensry.io
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# SPDX-License-Identifier: Apache-2.0
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description: Sensry SY1XX GPIO PORT node
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compatible: "sensry,sy1xx-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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description: Base address for the gpio configuration.
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"#gpio-cells":
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const: 2
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pad-cfg:
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type: int
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required: true
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description: Offset for gpio pad ctrl registers.
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gpio-cells:
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- pin
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- flags

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