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LucasTamborLucasTambor
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drivers: mbox: espressif: add esp32c6 support
Add support for esp32c6 HP and LP Core Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
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+75
-10
lines changed

4 files changed

+75
-10
lines changed

‎drivers/mbox/mbox_esp32.c

Lines changed: 35 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,20 @@
11
/*
22
* Copyright (c) 2024 Felipe Neves.
3+
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
34
*
45
* SPDX-License-Identifier: Apache-2.0
56
*/
67

78
#define DT_DRV_COMPAT espressif_mbox_esp32
9+
#if !defined(CONFIG_SOC_SERIES_ESP32C6)
810
#include "soc/dport_reg.h"
11+
#else
12+
#include <ulp_lp_core.h>
13+
#include <soc/pmu_reg.h>
14+
#include <ulp_lp_core_utils.h>
15+
#include <ulp_lp_core_interrupts.h>
16+
#endif
17+
918
#include "soc/gpio_periph.h"
1019

1120
#include <stdint.h>
@@ -64,12 +73,16 @@ IRAM_ATTR static void esp32_mbox_isr(const struct device *dev)
6473
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
6574
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
6675
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
76+
#elif defined(CONFIG_SOC_ESP32C6_HPCORE)
77+
SET_PERI_REG_MASK(PMU_HP_INT_CLR_REG, PMU_SW_INT_CLR);
6778
#endif
6879
} else {
6980
#if defined(CONFIG_SOC_SERIES_ESP32)
7081
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
7182
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
7283
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
84+
#elif defined(CONFIG_SOC_ESP32C6_LPCORE)
85+
ulp_lp_core_sw_intr_clear();
7386
#endif
7487
}
7588

@@ -116,23 +129,26 @@ static int esp32_mbox_send(const struct device *dev, mbox_channel_id_t channel,
116129
/* Only the lower 16bits of id are used */
117130
dev_data->control->dest_cpu_msg_id[dev_data->other_core_id] = (uint16_t)(channel & 0xFFFF);
118131

132+
atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL);
133+
119134
/* Generate interrupt in the remote core */
120135
if (dev_data->this_core_id == 0) {
121-
atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL);
122136
LOG_DBG("Generating interrupt on remote CPU 1 from CPU 0");
123137
#if defined(CONFIG_SOC_SERIES_ESP32)
124138
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
125139
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
126140
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
141+
#elif defined(CONFIG_SOC_ESP32C6_HPCORE)
142+
ulp_lp_core_sw_intr_trigger();
127143
#endif
128-
129144
} else {
130-
atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL);
131145
LOG_DBG("Generating interrupt on remote CPU 0 from CPU 1");
132146
#if defined(CONFIG_SOC_SERIES_ESP32)
133147
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
134148
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
135149
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
150+
#elif defined(CONFIG_SOC_ESP32C6_LPCORE)
151+
ulp_lp_core_wakeup_main_processor();
136152
#endif
137153
}
138154

@@ -197,6 +213,9 @@ static int esp32_mbox_init(const struct device *dev)
197213
int ret;
198214

199215
data->this_core_id = esp_core_id();
216+
#if defined(CONFIG_SOC_ESP32C6_LPCORE)
217+
data->this_core_id = 1;
218+
#endif
200219
data->other_core_id = (data->this_core_id == 0) ? 1 : 0;
201220

202221
LOG_DBG("Size of MBOX shared memory: %d", data->shm_size);
@@ -206,29 +225,40 @@ static int esp32_mbox_init(const struct device *dev)
206225

207226
/* pro_cpu is responsible to initialize the lock of shared memory */
208227
if (data->this_core_id == 0) {
228+
#if !defined(CONFIG_SOC_ESP32C6_LPCORE)
209229
ret = esp_intr_alloc(cfg->irq_source_pro_cpu,
210230
ESP_PRIO_TO_FLAGS(cfg->irq_priority_pro_cpu) |
211231
ESP_INT_FLAGS_CHECK(cfg->irq_flags_pro_cpu) |
212232
ESP_INTR_FLAG_IRAM,
213233
(intr_handler_t)esp32_mbox_isr, (void *)dev, NULL);
234+
#endif
235+
#if defined(CONFIG_SOC_ESP32C6_HPCORE)
236+
SET_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SW_INT_ENA);
237+
#endif
214238
atomic_set(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL);
215239
} else {
216240
/* app_cpu wait for initialization from pro_cpu, then takes it,
217241
* after that releases
218242
*/
243+
#if defined(CONFIG_SOC_ESP32C6_LPCORE)
244+
ret = 0;
245+
ulp_lp_core_intr_set_handler(cfg->irq_source_app_cpu,
246+
(void (*)(void *))esp32_mbox_isr, (void *)dev);
247+
ulp_lp_core_intr_enable();
248+
ulp_lp_core_sw_intr_enable(true);
249+
#else
219250
ret = esp_intr_alloc(cfg->irq_source_app_cpu,
220251
ESP_PRIO_TO_FLAGS(cfg->irq_priority_app_cpu) |
221252
ESP_INT_FLAGS_CHECK(cfg->irq_flags_app_cpu) |
222253
ESP_INTR_FLAG_IRAM,
223254
(intr_handler_t)esp32_mbox_isr, (void *)dev, NULL);
224-
255+
#endif
225256
LOG_DBG("Waiting CPU0 to sync");
226257
while (!atomic_cas(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL,
227258
data->this_core_id)) {
228259
}
229260

230261
atomic_set(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL);
231-
232262
LOG_DBG("Synchronization done");
233263
}
234264

‎dts/riscv/espressif/esp32c6/esp32c6_common.dtsi

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -106,11 +106,24 @@
106106
reg = <0x50000000 DT_SIZE_K(16)>;
107107
zephyr,memory-region = "SRAMLP ";
108108

109-
shmlp: memory@0 {
110-
reg = <0x0 0x10>;
109+
shmlp: memory@50003fe0 {
110+
reg = <0x50003fe0 0x10>;
111111
};
112112
};
113113

114+
mbox0: mbox@50003ff0 {
115+
compatible = "espressif,mbox-esp32";
116+
reg = <0x50003ff0 0x8>;
117+
status = "disabled";
118+
shared-memory = <&shmlp>;
119+
shared-memory-size = <0x10>;
120+
interrupts =
121+
<PMU_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
122+
<LP_CORE_PMU_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
123+
interrupt-parent = <&intc>;
124+
#mbox-cells = <1>;
125+
};
126+
114127
intc: interrupt-controller@60010000 {
115128
compatible = "espressif,esp32-intc";
116129
#address-cells = <0>;

‎dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -41,11 +41,33 @@
4141
compatible = "mmio-sram";
4242
reg = <0x50000000 DT_SIZE_K(16)>;
4343

44-
shmlp: memory@0 {
45-
reg = <0x0 0x10>;
44+
shmlp: memory@50003fb0{
45+
reg = <0x50003fb0 0x50>;
4646
};
4747
};
4848

49+
mbox0: mbox@50003ff0 {
50+
compatible = "espressif,mbox-esp32";
51+
reg = <0x50003ff0 0x8>;
52+
status = "disabled";
53+
shared-memory = <&shmlp>;
54+
shared-memory-size = <0x40>;
55+
interrupts =
56+
<PMU_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
57+
<LP_CORE_PMU_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
58+
interrupt-parent = <&intc>;
59+
#mbox-cells = <1>;
60+
};
61+
62+
intc: interrupt-controller@50000008 {
63+
compatible = "espressif,esp32-intc";
64+
#address-cells = <0>;
65+
#interrupt-cells = <3>;
66+
interrupt-controller;
67+
reg = <0x50000008 DT_SIZE_K(4)>;
68+
status = "okay";
69+
};
70+
4971
flash: flash-controller@60002000 {
5072
compatible = "espressif,esp32-flash-controller";
5173
reg = <0x60002000 0x1000>;

‎west.yml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,7 @@ manifest:
169169
groups:
170170
- hal
171171
- name: hal_espressif
172-
revision: f3453bdeced28642424692aae32cce4eec3f2d7f
172+
revision: pull/464/head
173173
path: modules/hal/espressif
174174
west-commands: west/west-commands.yml
175175
groups:

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