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drivers: gpio: Add support for cc23x0 GPIO
Add support for GPIO to cc23x0 SoC. Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com> Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com> Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com> Signed-off-by: Julien Panis <jpanis@baylibre.com>
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‎drivers/gpio/CMakeLists.txt

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@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711 gpio_bcm2711.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BD8LB600FS gpio_bd8lb600fs.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB gpio_brcmstb.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC23X0 gpio_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_CY8C95XX gpio_cy8c95xx.c)

‎drivers/gpio/Kconfig

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@@ -107,6 +107,7 @@ source "drivers/gpio/Kconfig.bcm2711"
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source "drivers/gpio/Kconfig.bd8lb600fs"
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source "drivers/gpio/Kconfig.brcmstb"
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source "drivers/gpio/Kconfig.cc13xx_cc26xx"
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source "drivers/gpio/Kconfig.cc23x0"
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source "drivers/gpio/Kconfig.cc32xx"
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source "drivers/gpio/Kconfig.cmsdk_ahb"
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source "drivers/gpio/Kconfig.creg_gpio"

‎drivers/gpio/Kconfig.cc23x0

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# Copyright (c) 2024 Texas Instruments Incorporated
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# Copyright (c) 2024 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_CC23X0
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bool "TI SimpleLink CC23X0 GPIO driver"
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default y
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depends on DT_HAS_TI_CC23X0_GPIO_ENABLED
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help
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Enable the TI SimpleLink CC23x0 GPIO driver.

‎drivers/gpio/gpio_cc23x0.c

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/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_gpio
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#include <zephyr/types.h>
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#include <zephyr/device.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <driverlib/clkctl.h>
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#include <driverlib/gpio.h>
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#include <inc/hw_ioc.h>
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#define IOC_ADDR(index) (IOC_BASE + IOC_O_IOC0 + (sizeof(uint32_t) * (index)))
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struct gpio_cc23x0_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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};
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struct gpio_cc23x0_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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};
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static void set_pin_mask_non_atomic(uint8_t index, uint32_t registerBaseAddress)
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{
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GPIOSetConfigDio(GPIO_BASE + registerBaseAddress, BIT(index));
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}
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static int gpio_cc23x0_config(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
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{
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uint32_t config = 0;
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uint32_t iocfg_reg = IOC_ADDR(pin);
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gpio_flags_t direction = flags & GPIO_DIR_MASK;
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if (flags & GPIO_PULL_UP) {
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config |= IOC_IOC0_PULLCTL_PULL_UP;
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} else if (flags & GPIO_PULL_DOWN) {
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config |= IOC_IOC0_PULLCTL_PULL_DOWN;
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} else {
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config |= IOC_IOC0_PULLCTL_PULL_DIS;
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}
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if (!(flags & GPIO_SINGLE_ENDED)) {
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config |= IOC_IOC0_IOMODE_NORMAL;
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} else {
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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config |= IOC_IOC0_IOMODE_OPEND;
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} else {
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config |= IOC_IOC0_IOMODE_OPENS;
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}
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}
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if (direction & GPIO_INPUT) {
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config |= IOC_IOC0_INPEN_EN | IOC_IOC0_HYSTEN_EN;
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}
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GPIOSetConfigDio(iocfg_reg, config);
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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GPIOSetDio(pin);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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GPIOClearDio(pin);
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}
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GPIOSetOutputEnableDio(pin, GPIO_OUTPUT_ENABLE);
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} else {
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GPIOSetOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
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}
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return 0;
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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static int gpio_cc23x0_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
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{
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uint32_t out_flag = 0;
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uint32_t iocfg_reg = IOC_ADDR(pin);
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uint32_t config = GPIOGetConfigDio(iocfg_reg);
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/* GPIO input/output configuration flags */
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if (config & IOC_IOC0_INPEN_EN) {
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out_flag |= GPIO_INPUT;
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}
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if (GPIOGetOutputEnableDio(pin)) {
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out_flag |= GPIO_OUTPUT;
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if (GPIOReadDio(pin)) {
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out_flag |= GPIO_OUTPUT_INIT_HIGH;
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} else {
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/* This is the default value. If not explicitly set,
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* the returned config will not be symmetric
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*/
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out_flag |= GPIO_OUTPUT_INIT_LOW;
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}
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}
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/* GPIO interrupt configuration flags */
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if ((config & IOC_IOC0_EDGEDET_M) != IOC_IOC0_EDGEDET_EDGE_DIS) {
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if (config & IOC_IOC0_EDGEDET_EDGE_POS) {
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out_flag |= GPIO_INT_EDGE_RISING;
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}
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if (config & IOC_IOC0_EDGEDET_EDGE_NEG) {
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out_flag |= GPIO_INT_EDGE_FALLING;
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}
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} else {
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/* This is the default value. If not explicitly set,
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* the returned config will not be symmetric
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*/
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out_flag |= GPIO_INT_DISABLE;
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}
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/* GPIO pin drive flags */
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if (config & IOC_IOC0_IOMODE_OPENS) {
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out_flag |= GPIO_OPEN_SOURCE;
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}
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if (config & IOC_IOC0_IOMODE_OPEND) {
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out_flag |= IOC_IOC0_IOMODE_OPEND;
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}
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if (config & IOC_IOC0_PULLCTL_PULL_UP) {
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out_flag |= GPIO_PULL_UP;
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}
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if (config & IOC_IOC0_PULLCTL_PULL_DOWN) {
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out_flag |= GPIO_PULL_DOWN;
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}
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*flags = out_flag;
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return 0;
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}
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#endif
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static int gpio_cc23x0_port_get_raw(const struct device *port, uint32_t *value)
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{
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*value = GPIOReadMultiDio(GPIO_DIO_ALL_MASK);
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return 0;
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}
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static int gpio_cc23x0_port_set_masked_raw(const struct device *port, uint32_t mask, uint32_t value)
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{
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GPIOWriteMultiDio(mask, value);
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return 0;
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}
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static int gpio_cc23x0_port_set_bits_raw(const struct device *port, uint32_t mask)
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{
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GPIOSetMultiDio(mask);
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return 0;
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}
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static int gpio_cc23x0_port_clear_bits_raw(const struct device *port, uint32_t mask)
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{
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GPIOClearMultiDio(mask);
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return 0;
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}
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static int gpio_cc23x0_port_toggle_bits(const struct device *port, uint32_t mask)
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{
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GPIOToggleMultiDio(mask);
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return 0;
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}
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static int gpio_cc23x0xx_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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if (mode == GPIO_INT_MODE_LEVEL) {
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return ENOTSUP;
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}
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uint32_t config = GPIOGetConfigDio(IOC_ADDR(pin)) & ~IOC_IOC0_EDGEDET_M;
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if (mode == GPIO_INT_MODE_DISABLED) {
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config |= IOC_IOC1_EDGEDET_EDGE_DIS;
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GPIOSetConfigDio(IOC_ADDR(pin), config);
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/* Disable interrupt mask */
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set_pin_mask_non_atomic(pin, GPIO_O_IMCLR);
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} else if (mode == GPIO_INT_MODE_EDGE) {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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config |= IOC_IOC1_EDGEDET_EDGE_NEG;
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break;
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case GPIO_INT_TRIG_HIGH:
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config |= IOC_IOC1_EDGEDET_EDGE_POS;
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break;
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case GPIO_INT_TRIG_BOTH:
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config |= IOC_IOC1_EDGEDET_EDGE_BOTH;
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break;
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default:
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return ENOTSUP;
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}
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GPIOSetConfigDio(IOC_ADDR(pin), config);
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/* Enable interrupt mask */
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set_pin_mask_non_atomic(pin, GPIO_O_ICLR);
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set_pin_mask_non_atomic(pin, GPIO_O_IMSET);
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}
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return 0;
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}
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static int gpio_cc23x0_manage_callback(const struct device *port, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_cc23x0_data *data = port->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static uint32_t gpio_cc23x0_get_pending_int(const struct device *dev)
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{
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return GPIOGetEventMultiDio(GPIO_DIO_ALL_MASK);
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}
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static void gpio_cc23x0_isr(const struct device *dev)
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{
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struct gpio_cc23x0_data *data = dev->data;
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uint32_t status = GPIOGetEventMultiDio(GPIO_DIO_ALL_MASK);
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GPIOClearEventMultiDio(status);
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gpio_fire_callbacks(&data->callbacks, dev, status);
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}
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static int gpio_cc23x0_init(const struct device *dev)
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{
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/* Enable GPIO domain clock */
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CLKCTLEnable(CLKCTL_BASE, CLKCTL_GPIO);
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/* Enable IRQ */
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), gpio_cc23x0_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(DT_INST_IRQN(0));
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return 0;
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}
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static const struct gpio_driver_api gpio_cc23x0_driver_api = {
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.pin_configure = gpio_cc23x0_config,
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#ifdef CONFIG_GPIO_GET_CONFIG
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.pin_get_config = gpio_cc23x0_get_config,
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#endif
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.port_get_raw = gpio_cc23x0_port_get_raw,
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.port_set_masked_raw = gpio_cc23x0_port_set_masked_raw,
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.port_set_bits_raw = gpio_cc23x0_port_set_bits_raw,
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.port_clear_bits_raw = gpio_cc23x0_port_clear_bits_raw,
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.port_toggle_bits = gpio_cc23x0_port_toggle_bits,
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.pin_interrupt_configure = gpio_cc23x0xx_pin_interrupt_configure,
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.manage_callback = gpio_cc23x0_manage_callback,
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.get_pending_int = gpio_cc23x0_get_pending_int,
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};
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static const struct gpio_cc23x0_config gpio_cc23x0_config_0 = {
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.common = {/* Read ngpios from DT */
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}};
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static struct gpio_cc23x0_data gpio_cc23x0_data_0;
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DEVICE_DT_INST_DEFINE(0, gpio_cc23x0_init, NULL, &gpio_cc23x0_data_0, &gpio_cc23x0_config_0,
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_cc23x0_driver_api);

‎dts/bindings/gpio/ti,cc23x0-gpio.yaml

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# Copyright (c) 2024 Texas Instruments Incorporated
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# Copyright (c) 2024 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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description: TI SimpleLink CC23X0 GPIO node
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compatible: "ti,cc23x0-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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"#gpio-cells":
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const: 2
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gpio-cells:
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- pin
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- flags

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