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Zoe Kaute
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drivers: crc: Add hardware-based CRC driver
Adds support for hardware-based CRC-8-CCITT and CRC-32-IEEE calculations. Signed-off-by: Zoe Kaute <zoe.kaute@brillpower.com>
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‎MAINTAINERS.yml

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tests:
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- drivers.counter
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"Drivers: CRC":
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status: maintained
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maintainers:
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- zkat2
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files:
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- drivers/crc/
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- dts/bindings/crc/
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- include/zephyr/drivers/crc.h
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- samples/drivers/crc/
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- tests/drivers/crc/
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- doc/hardware/peripherals/crc.rst
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labels:
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- "area: CRC"
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tests:
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- drivers.crc
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"Drivers: Crypto":
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status: maintained
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maintainers:

‎doc/hardware/peripherals/crc.rst

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.. _crc_api:
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Cyclic Redundancy Check (CRC)
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#############################
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Overview
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********
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The Cyclic Redundancy Check (CRC) API provides functions for configuring and computing CRC values
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on hardware.
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Configuration Options
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*********************
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Related configuration options:
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* :kconfig:option:`CRC_INIT_PRIORITY`
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API Reference
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*************
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.. doxygengroup:: crc_interface

‎doc/hardware/peripherals/index.rst

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charger.rst
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coredump.rst
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counter.rst
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crc.rst
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dac.rst
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dma.rst
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display/index.rst

‎drivers/CMakeLists.txt

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@@ -26,6 +26,7 @@ add_subdirectory_ifdef(CONFIG_CLOCK_CONTROL clock_control)
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add_subdirectory_ifdef(CONFIG_CONSOLE console)
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add_subdirectory_ifdef(CONFIG_COREDUMP_DEVICE coredump)
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add_subdirectory_ifdef(CONFIG_COUNTER counter)
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add_subdirectory_ifdef(CONFIG_CRC_HW crc)
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add_subdirectory_ifdef(CONFIG_CRYPTO crypto)
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add_subdirectory_ifdef(CONFIG_DAC dac)
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add_subdirectory_ifdef(CONFIG_DAI dai)

‎drivers/Kconfig

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@@ -18,6 +18,7 @@ source "drivers/clock_control/Kconfig"
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source "drivers/console/Kconfig"
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source "drivers/coredump/Kconfig"
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source "drivers/counter/Kconfig"
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source "drivers/crc/Kconfig"
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source "drivers/crypto/Kconfig"
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source "drivers/dac/Kconfig"
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source "drivers/dai/Kconfig"

‎drivers/crc/CMakeLists.txt

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# Copyright (c) 2024 Brill Power Ltd.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CRC_STM32 crc_stm32.c)

‎drivers/crc/Kconfig

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# Copyright (c) 2024 Brill Power Ltd.
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# SPDX-License-Identifier: Apache-2.0
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menuconfig CRC_HW
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bool "CRC HW acceleration"
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if CRC_HW
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module = CRC_HW
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module-str = CRC_HW
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source "subsys/logging/Kconfig.template.log_config"
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config CRC_INIT_PRIORITY
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int "CRC init priority"
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default KERNEL_INIT_PRIORITY_DEVICE
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help
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CRC driver device initialization priority.
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source "drivers/crc/Kconfig.stm32"
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endif # CRC_HW

‎drivers/crc/Kconfig.stm32

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# Copyright (c) 2024 Brill Power Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config CRC_STM32
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bool
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default y
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depends on DT_HAS_ST_STM32_CRC_ENABLED
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help
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Enable the driver implementation for STM32 microcontrollers

‎drivers/crc/crc_stm32.c

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/*
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* Copyright (c) 2024 Brill Power Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(crc_stm32, CONFIG_CRC_HW_LOG_LEVEL);
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/crc.h>
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#include <zephyr/sys/byteorder.h>
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#include <soc.h>
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#include <stm32_ll_crc.h>
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#define DT_DRV_COMPAT st_stm32_crc
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struct crc_stm32_cfg {
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CRC_TypeDef *base;
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struct stm32_pclken pclken;
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};
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struct crc_stm32_data {
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struct k_sem sem;
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};
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static void crc_lock(const struct device *dev)
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{
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struct crc_stm32_data *data = (struct crc_stm32_data *)dev->data;
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k_sem_take(&data->sem, K_FOREVER);
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}
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static void crc_unlock(const struct device *dev)
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{
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struct crc_stm32_data *data = (struct crc_stm32_data *)dev->data;
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k_sem_give(&data->sem);
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}
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static int crc_stm32_begin(const struct device *dev, struct crc_ctx *ctx)
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{
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/* Attempt to take semaphore */
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crc_lock(dev);
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/* Ensure ctx is not currently being updated */
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if (ctx->state == CRC_STATE_IN_PROGRESS) {
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crc_unlock(dev);
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return -EBUSY;
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}
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ctx->state = CRC_STATE_IN_PROGRESS; /* Indicate calculation in progress */
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const struct crc_stm32_cfg *cfg = dev->config;
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LL_CRC_SetInputDataReverseMode(cfg->base, (ctx->flags & CRC_FLAG_REVERSE_INPUT)
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? LL_CRC_INDATA_REVERSE_WORD
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: LL_CRC_INDATA_REVERSE_NONE);
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LL_CRC_SetOutputDataReverseMode(cfg->base, (ctx->flags & CRC_FLAG_REVERSE_OUTPUT)
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? LL_CRC_OUTDATA_REVERSE_BIT
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: LL_CRC_INDATA_REVERSE_NONE);
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LL_CRC_ResetCRCCalculationUnit(cfg->base);
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switch (ctx->type) {
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case CRC8_CCITT_HW: {
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uint8_t init_val = (uint8_t)(ctx->initial_value & 0xFF);
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uint8_t poly = (uint8_t)(ctx->polynomial & 0xFF);
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LL_CRC_SetPolynomialSize(cfg->base, LL_CRC_POLYLENGTH_8B);
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LL_CRC_SetPolynomialCoef(cfg->base, poly);
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LL_CRC_SetInitialData(cfg->base, init_val);
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break;
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}
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case CRC32_IEEE_HW: {
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uint32_t init_val = (uint32_t)(ctx->initial_value & 0xFFFFFFFF);
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uint32_t poly = (uint32_t)(ctx->polynomial & 0xFFFFFFFF);
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LL_CRC_SetPolynomialSize(cfg->base, LL_CRC_POLYLENGTH_32B);
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LL_CRC_SetPolynomialCoef(cfg->base, poly);
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LL_CRC_SetInitialData(cfg->base, init_val);
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break;
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}
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default:
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ctx->state = CRC_STATE_IDLE;
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crc_unlock(dev);
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return -ENOTSUP;
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}
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return 0;
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}
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static int crc_stm32_update(const struct device *dev, struct crc_ctx *ctx, const void *buffer,
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size_t bufsize)
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{
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/* Ensure CRC calculation has been initialized by crc_begin() */
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if (ctx->state == CRC_STATE_IDLE) {
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return -EINVAL;
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}
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const struct crc_stm32_cfg *cfg = dev->config;
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const uint8_t *buf = buffer;
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switch (ctx->type) {
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case CRC8_CCITT_HW: {
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register uint32_t index = 0;
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for (index = 0; index < bufsize; index++) {
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LL_CRC_FeedData8(cfg->base, buf[index]);
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}
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uint8_t result = LL_CRC_ReadData8(cfg->base);
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ctx->result = (crc_result_t)result;
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break;
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}
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case CRC32_IEEE_HW: {
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register uint32_t crc_data = 0;
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register uint32_t index = 0;
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/* Compute the CRC of Data Buffer array*/
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for (index = 0; index < (bufsize / 4); index++) {
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crc_data = sys_get_le32(buf + 4 * index);
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LL_CRC_FeedData32(cfg->base, crc_data);
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}
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/* Last bytes specific handling */
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if ((bufsize & 3) != 0) {
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if ((bufsize & 3) == 3) {
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LL_CRC_FeedData16(cfg->base, sys_get_le16(buf + 4 * index));
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LL_CRC_FeedData8(cfg->base, buf[4 * index + 2]);
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} else if ((bufsize & 3) == 2) {
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LL_CRC_FeedData16(cfg->base, sys_get_le16(buf + 4 * index));
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} else { /* ((bufsize & 3) == 1) */
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LL_CRC_FeedData8(cfg->base, buf[4 * index]);
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}
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}
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uint32_t result = (~LL_CRC_ReadData32(cfg->base));
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ctx->result = (crc_result_t)result;
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break;
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}
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default:
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ctx->state = CRC_STATE_IDLE;
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crc_unlock(dev);
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return -ENOTSUP;
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}
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return 0;
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}
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static int crc_stm32_finish(const struct device *dev, struct crc_ctx *ctx)
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{
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/* Ensure CRC calculation is in progress */
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if (ctx->state == CRC_STATE_IDLE) {
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return -EINVAL;
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}
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ctx->state = CRC_STATE_IDLE; /* Indicate calculation done */
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crc_unlock(dev);
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return 0;
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}
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/**
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* @brief Called by Zephyr when instantiating device during boot
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* @param dev Pointer to the device structure for the driver instance.
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* @retval 0 On success
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* @retval -ENODEV Clock control device is not ready
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* @retval -EIO Fail to turn on appropriate clock for CRC instance
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*/
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static int crc_stm32_init(const struct device *dev)
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{
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const struct crc_stm32_cfg *cfg = dev->config;
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const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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if (!device_is_ready(clk)) {
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LOG_ERR("CRC: Clock control device not ready");
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return -ENODEV;
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}
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if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
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LOG_ERR("CRC: Clock control device could not initialise");
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return -EIO;
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}
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struct crc_stm32_data *data = dev->data;
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k_sem_init(&data->sem, 1, 1);
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return 0;
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}
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static const struct crc_driver_api crc_stm32_driver_api = {
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.crc_begin = crc_stm32_begin,
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.crc_update = crc_stm32_update,
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.crc_finish = crc_stm32_finish,
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};
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#define STM32_CRC_INIT(index) \
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\
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static const struct crc_stm32_cfg crc_stm32_cfg_##index = { \
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.base = (CRC_TypeDef *)DT_INST_REG_ADDR(index), \
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.pclken = \
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{ \
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.enr = DT_INST_CLOCKS_CELL(index, bits), \
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.bus = DT_INST_CLOCKS_CELL(index, bus), \
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}, \
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}; \
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\
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static struct crc_stm32_data crc_stm32_data_##index = {}; \
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\
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DEVICE_DT_INST_DEFINE(index, &crc_stm32_init, NULL, &crc_stm32_data_##index, \
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&crc_stm32_cfg_##index, POST_KERNEL, CONFIG_CRC_INIT_PRIORITY, \
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&crc_stm32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(STM32_CRC_INIT)

‎dts/bindings/crc/st,stm32-crc.yaml

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# Copyright (c) 2024 Brill Power Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: ST STM32 family CRC
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compatible: "st,stm32-crc"
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include: [base.yaml]
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properties:
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reg:
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required: true
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clocks:
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type: phandle-array
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required: true
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description: Clock information

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