arch/xtensa: Rename "ALLOCA" ZSR to "A0SAVE"

This register alias was originally introduced to allow A0 to be used
as a scratch register when handling exceptions from MOVSP
instructions. (It replaced some upstream code from Cadence that
hard-coded EXCSAVE1).  Now the MMU code is now using too, and for
exactly the same purpose.

Calling it "ALLOCA" is only confusing.  Rename it to make it clear
what it's doing.

Signed-off-by: Andy Ross <andyross@google.com>

Author: andyross

arch/xtensa/core/gen_zsr.py

@@ -11,7 +11,7 @@
 # -dM") core-isa.h file for the current architecture and assigns
 # registers to usages.
 
-NEEDED = ("ALLOCA", "CPU", "FLUSH")
+NEEDED = ("A0SAVE", "CPU", "FLUSH")
 
 coreisa = sys.argv[1]
 outfile = sys.argv[2]

arch/xtensa/core/window_vectors.S

@@ -84,7 +84,7 @@ _WindowUnderflow4:
 /* Handle alloca exception generated by interruptee executing 'movsp'.
  * This uses space between the window vectors, so is essentially
  * "free".  All interruptee's regs are intact except a0 which is saved
- * in $ZSR_ALLOCA (assigned at build time, see gen_zsr.py for
+ * in $ZSR_A0SAVE (assigned at build time, see gen_zsr.py for
  * details), and PS.EXCM has been set by the exception hardware (can't
  * be interrupted).  The fact the alloca exception was taken means the
  * registers associated with the base-save area have been spilled and
@@ -102,7 +102,7 @@ _xt_alloca_exc:
     rsr     a2, PS
     extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
     xor     a3, a3, a4    /* bits changed from old to current windowbase */
-    rsr     a4, ZSR_ALLOCA  /* restore original a0 (now in a4) */
+    rsr     a4, ZSR_A0SAVE  /* restore original a0 (now in a4) */
     slli    a3, a3, XCHAL_PS_OWB_SHIFT
     xor     a2, a2, a3      /* flip changed bits in old window base */
     wsr     a2, PS          /* update PS.OWB to new window base */

arch/xtensa/core/xtensa-asm2-util.S

@@ -342,7 +342,7 @@ DEF_EXCINT XCHAL_DEBUGLEVEL, _handle_excint, xtensa_debugint_c
 .pushsection .UserExceptionVector.text, "ax"
 .global _Level1RealVector
 _Level1RealVector:
-	wsr a0, ZSR_ALLOCA
+	wsr a0, ZSR_A0SAVE
 	rsync
 	rsr.exccause a0
 #ifdef CONFIG_XTENSA_MMU
@@ -355,7 +355,7 @@ _Level1RealVector:
 
 	j _xt_alloca_exc
 _not_alloca:
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 	j _Level1Vector
 #ifdef CONFIG_XTENSA_MMU
 _handle_tlb_miss_user:
@@ -374,7 +374,7 @@ _handle_tlb_miss_user:
 	 */
 	rsr.ptevaddr a0
 	l32i a0, a0, 0
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 	rfe
 #endif /* CONFIG_XTENSA_MMU */
 .popsection
@@ -391,12 +391,12 @@ _handle_tlb_miss_user:
 .global _KernelExceptionVector
 _KernelExceptionVector:
 #ifdef CONFIG_XTENSA_MMU
-	wsr a0, ZSR_ALLOCA
+	wsr a0, ZSR_A0SAVE
 	rsr.exccause a0
 	beqi a0, EXCCAUSE_ITLB_MISS, _handle_tlb_miss_kernel
 	addi a0, a0, -EXCCAUSE_DTLB_MISS
 	beqz a0, _handle_tlb_miss_kernel
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 #endif
 	j _Level1Vector
 #ifdef CONFIG_XTENSA_MMU
@@ -410,7 +410,7 @@ _handle_tlb_miss_kernel:
 	 */
 	rsr.ptevaddr a0
 	l32i a0, a0, 0
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 	rfe
 #endif
 .popsection
@@ -420,14 +420,14 @@ _handle_tlb_miss_kernel:
 .global _DoubleExceptionVector
 _DoubleExceptionVector:
 #ifdef CONFIG_XTENSA_MMU
-	wsr a0, ZSR_ALLOCA
+	wsr a0, ZSR_A0SAVE
 	rsync
 
 	rsr.exccause a0
 	addi a0, a0, -EXCCAUSE_DTLB_MISS
 	beqz a0, _handle_tlb_miss_dblexc
 
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 #endif
 #if defined(CONFIG_SIMULATOR_XTENSA) || defined(XT_SIMULATOR)
 1:
@@ -459,7 +459,7 @@ _handle_tlb_miss_dblexc:
 	rsr.ptevaddr a0
 	l32i a0, a0, 0
 
-	rsr a0, ZSR_ALLOCA
+	rsr a0, ZSR_A0SAVE
 	rfde
 #endif
 .popsection