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| 1 | +/* |
| 2 | + * Copyright (c) 2025 TOKITA Hiroshi |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#define DT_DRV_COMPAT brcm_iproc_rng200 |
| 8 | + |
| 9 | +#include <zephyr/logging/log.h> |
| 10 | +LOG_MODULE_REGISTER(iproc_rng200_entropy, CONFIG_ENTROPY_LOG_LEVEL); |
| 11 | + |
| 12 | +#include <zephyr/device.h> |
| 13 | +#include <zephyr/drivers/entropy.h> |
| 14 | +#include <errno.h> |
| 15 | +#include <zephyr/init.h> |
| 16 | +#include <zephyr/kernel.h> |
| 17 | + |
| 18 | +#define IPROC_RNG200_CTRL_OFFS 0x00 |
| 19 | +#define IPROC_RNG200_RNG_RESET_OFFS 0x04 |
| 20 | +#define IPROC_RNG200_RBG_RESET_OFFS 0x08 |
| 21 | +#define IPROC_RNG200_RESERVED1_OFFS 0x0c |
| 22 | +#define IPROC_RNG200_RESERVED2_OFFS 0x10 |
| 23 | +#define IPROC_RNG200_RESERVED3_OFFS 0x14 |
| 24 | +#define IPROC_RNG200_INT_STATUS_OFFS 0x18 |
| 25 | +#define IPROC_RNG200_RESERVED4_OFFS 0x1c |
| 26 | +#define IPROC_RNG200_FIFO_DATA_OFFS 0x20 |
| 27 | +#define IPROC_RNG200_FIFO_COUNT_OFFS 0x24 |
| 28 | + |
| 29 | +#define IPROC_RNG200_CTRL_RBG_EN BIT(0) |
| 30 | +#define IPROC_RNG200_RESET_EN BIT(0) |
| 31 | +#define IPROC_RNG200_INT_STATUS_NIST_FAIL BIT(5) |
| 32 | +#define IPROC_RNG200_INT_STATUS_MASTER_FAIL_LOCKOUT BIT(31) |
| 33 | + |
| 34 | +#define IPROC_RNG200_CTRL_RBG_EN_MASK BIT_MASK(13) |
| 35 | +#define IPROC_RNG200_FIFO_COUNT_MASK BIT_MASK(8) |
| 36 | + |
| 37 | +/* time needed to fill fifo when empty */ |
| 38 | +#define IPROC_RNG200_FIFO_REFILL_TIME_USEC 40 |
| 39 | +#define IPROC_RNG200_FIFO_REFILL_MAX_RETRIES 5 |
| 40 | + |
| 41 | +#define DEV_CFG(dev) ((const struct iproc_rng200_config *)(dev)->config) |
| 42 | +#define DEV_DATA(dev) ((struct iproc_rng200_data *)(dev)->data) |
| 43 | + |
| 44 | +struct iproc_rng200_config { |
| 45 | + DEVICE_MMIO_NAMED_ROM(base_addr); |
| 46 | +}; |
| 47 | + |
| 48 | +struct iproc_rng200_data { |
| 49 | + DEVICE_MMIO_NAMED_RAM(base_addr); |
| 50 | + struct k_mutex mutex; |
| 51 | +}; |
| 52 | + |
| 53 | +static int iproc_rng200_driver_init(const struct device *dev) |
| 54 | +{ |
| 55 | + struct iproc_rng200_data *const data = dev->data; |
| 56 | + |
| 57 | + k_mutex_init(&data->mutex); |
| 58 | + |
| 59 | + DEVICE_MMIO_NAMED_MAP(dev, base_addr, K_MEM_CACHE_NONE); |
| 60 | + |
| 61 | + const mem_addr_t base = DEVICE_MMIO_NAMED_GET(dev, base_addr); |
| 62 | + const uint32_t val = |
| 63 | + sys_read32(base + IPROC_RNG200_CTRL_OFFS) & IPROC_RNG200_CTRL_RBG_EN_MASK; |
| 64 | + |
| 65 | + sys_write32(val & ~IPROC_RNG200_CTRL_RBG_EN, base + IPROC_RNG200_CTRL_OFFS); |
| 66 | + |
| 67 | + return 0; |
| 68 | +} |
| 69 | + |
| 70 | +static int iproc_rng200_driver_get_entropy(const struct device *dev, uint8_t *buffer, |
| 71 | + uint16_t length) |
| 72 | +{ |
| 73 | + const mem_addr_t base = DEVICE_MMIO_NAMED_GET(dev, base_addr); |
| 74 | + const uint32_t word_count = DIV_ROUND_UP(length, 4); |
| 75 | + struct iproc_rng200_data *const data = dev->data; |
| 76 | + uint32_t retries_left; |
| 77 | + uint32_t random_word; |
| 78 | + |
| 79 | + for (uint32_t i = 0; i < word_count; i++) { |
| 80 | + retries_left = IPROC_RNG200_FIFO_REFILL_MAX_RETRIES; |
| 81 | + k_mutex_lock(&data->mutex, K_FOREVER); |
| 82 | + |
| 83 | + while (true) { |
| 84 | + const uint32_t status = sys_read32(base + IPROC_RNG200_INT_STATUS_OFFS); |
| 85 | + uint32_t val; |
| 86 | + |
| 87 | + if (status & (IPROC_RNG200_INT_STATUS_MASTER_FAIL_LOCKOUT | |
| 88 | + IPROC_RNG200_INT_STATUS_NIST_FAIL)) { |
| 89 | + |
| 90 | + sys_write32(0xFFFFFFFF, base + IPROC_RNG200_INT_STATUS_OFFS); |
| 91 | + |
| 92 | + val = sys_read32(base + IPROC_RNG200_RNG_RESET_OFFS); |
| 93 | + sys_write32(val | IPROC_RNG200_RESET_EN, |
| 94 | + base + IPROC_RNG200_RNG_RESET_OFFS); |
| 95 | + |
| 96 | + val = sys_read32(base + IPROC_RNG200_RBG_RESET_OFFS); |
| 97 | + sys_write32(val | IPROC_RNG200_RESET_EN, |
| 98 | + base + IPROC_RNG200_RBG_RESET_OFFS); |
| 99 | + |
| 100 | + val = sys_read32(base + IPROC_RNG200_RNG_RESET_OFFS); |
| 101 | + sys_write32(val & ~IPROC_RNG200_RESET_EN, |
| 102 | + base + IPROC_RNG200_RNG_RESET_OFFS); |
| 103 | + |
| 104 | + val = sys_read32(base + IPROC_RNG200_RBG_RESET_OFFS); |
| 105 | + sys_write32(val & ~IPROC_RNG200_RESET_EN, |
| 106 | + base + IPROC_RNG200_RBG_RESET_OFFS); |
| 107 | + } |
| 108 | + |
| 109 | + /* make sure fifo has at least one random word */ |
| 110 | + const uint32_t fcnt = sys_read32(base + IPROC_RNG200_FIFO_COUNT_OFFS); |
| 111 | + |
| 112 | + if ((fcnt & IPROC_RNG200_FIFO_COUNT_MASK) > 0) { |
| 113 | + /* get new random word */ |
| 114 | + random_word = sys_read32(base + IPROC_RNG200_FIFO_DATA_OFFS); |
| 115 | + break; |
| 116 | + } |
| 117 | + |
| 118 | + /* currently no random values available, thus wait */ |
| 119 | + retries_left--; |
| 120 | + if (!retries_left) { |
| 121 | + /* number of retries exhausted, give up */ |
| 122 | + k_mutex_unlock(&data->mutex); |
| 123 | + return -ETIMEDOUT; |
| 124 | + } |
| 125 | + |
| 126 | + k_sleep(K_USEC(IPROC_RNG200_FIFO_REFILL_TIME_USEC)); |
| 127 | + } |
| 128 | + |
| 129 | + k_mutex_unlock(&data->mutex); |
| 130 | + |
| 131 | + memcpy(&buffer[i * 4], &random_word, MIN(length, 4)); |
| 132 | + length -= 4; |
| 133 | + } |
| 134 | + |
| 135 | + return 0; |
| 136 | +} |
| 137 | + |
| 138 | +static DEVICE_API(entropy, iproc_rng200_entropy_api) = { |
| 139 | + .get_entropy = iproc_rng200_driver_get_entropy, |
| 140 | +}; |
| 141 | + |
| 142 | +#define IPROC_RNG200_INIT(n) \ |
| 143 | + static const struct iproc_rng200_config iproc_rng200_##n##_cfg = { \ |
| 144 | + DEVICE_MMIO_NAMED_ROM_INIT(base_addr, DT_DRV_INST(n)), \ |
| 145 | + }; \ |
| 146 | + static struct iproc_rng200_data iproc_rng200_##n##_data; \ |
| 147 | + \ |
| 148 | + DEVICE_DT_INST_DEFINE(n, iproc_rng200_driver_init, NULL, &iproc_rng200_##n##_data, \ |
| 149 | + &iproc_rng200_##n##_cfg, PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY, \ |
| 150 | + &iproc_rng200_entropy_api); |
| 151 | + |
| 152 | +DT_INST_FOREACH_STATUS_OKAY(IPROC_RNG200_INIT) |
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