boards: shields: Support panel g1120b0mipi and rk055hdmipi4ma0 on RT700

Add board specific overlay and configuration for display panel
g1120b0mipi and rk055hdmipi4ma0.

Signed-off-by: Kate Wang <yumeng.wang@nxp.com>

Author: KATE-WANG-NXP

boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf

@@ -0,0 +1,2 @@
+CONFIG_REGULATOR=y
+CONFIG_DCACHE=n

boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay

@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <zephyr/dt-bindings/display/panel.h>
+
+&zephyr_lcdif {
+	status = "okay";
+	clock-frequency = <279000000>;
+	wr-period = <14>;
+	wr-assert = <6>;
+	wr-deassert = <13>;
+	cs-assert = <1>;
+	cs-deassert = <4>;
+};

boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf

@@ -0,0 +1,5 @@
+CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM=y
+CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR=0x60000000
+CONFIG_MCUX_DCNANO_LCDIF_MAINTAIN_CACHE=n
+CONFIG_HEAP_MEM_POOL_SIZE=40000
+CONFIG_REGULATOR=y

boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay

@@ -0,0 +1,21 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&zephyr_lcdif {
+	compatible = "nxp,dcnano-lcdif";
+	version = "DC8000";
+	display-timings {
+		clock-frequency = <29333333>;
+	};
+};
+
+&zephyr_mipi_dsi {
+	/* Use lower DPHY clock since RT700 uses AUDIO pll pfd2 as source,
+	 * and its max allowed clock frequency is
+	 * 532.48 x 18 / 16 = 599.04MHz. In this case the 60fps cannot be used, use 30fps instead.
+	 */
+	phy-clock = <396000000>;
+};