soc: ite: it51xxx: Prevent floating FSPI pins by enabling tri-state

To prevent FSPI pins from floating, which may cause internal leakage
and increase SoC power consumption, tri-state is enabled by default.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>

Author: GTLin08

soc/ite/ec/it51xxx/chip_chipregs.h

@@ -75,6 +75,11 @@ struct smfi_it51xxx_regs {
 #define SCARH_ENABLE                    BIT(7)
 #define SCARH_ADDR_BIT19                BIT(3)
 
+#define IT51XXX_SMFI_BASE      0xf01000
+/* 0x63: Flash Control Register 3 */
+#define IT51XXX_SMFI_FLHCTRL3R (IT51XXX_SMFI_BASE + 0x63)
+#define IT51XXX_SMFI_FFSPITRI  BIT(0)
+
 /**
  *
  * (16xxh) General Purpose I/O Port (GPIO) registers

soc/ite/ec/it51xxx/soc.c

@@ -117,6 +117,10 @@ void soc_prep_hook(void)
 	struct gpio_ite_ec_regs *const gpio_regs = GPIO_ITE_EC_REGS_BASE;
 	struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
 
+	/* Set FSPI pins are tri-state */
+	sys_write8(sys_read8(IT51XXX_SMFI_FLHCTRL3R) | IT51XXX_SMFI_FFSPITRI,
+		   IT51XXX_SMFI_FLHCTRL3R);
+
 	/* Scratch SRAM0 uses the 4KB based form 0x801000h */
 	gctrl_regs->GCTRL_SCR0BAR = IT51XXX_SEL_SRAM0_BASE_4K;