drivers: ethernet: Add platform driver for MMIO mapping reuse

The Ethernet device model consists of multiple subsystem components, such
as MDIO, PHY, MAC and PTP_CLOCK. These components are are mapped into a
single PCIe BAR location with same base address.

This platform driver retrieves the MMIO mapping details and provides a
framework to share them with all the child subsystem components. This
approach ensures efficient re-use of MMIO mappings across related
devices.

Example device tree structure for first ethernet instance:

parent0: parent0 {
        compatible = "intel,eth-plat";
        vendor-id  = <0x8086>;
        device-id  = <0xXXXX>;

        igc0: igc0 {
                compatible = "intel,igc-mac";
                interrupt-parent = <&intc>;

                /*
                 * MAC specific properties.
                 */

                status = "okay";
        };

        mdio0: mdio0 {
                compatible = "intel,igc-mdio";
                #address-cells = <1>;
                #size-cells = <0>;

                ethphy0: igc-phy@0 {
                        compatible = "intel,igc-phy";
                        /*
                         * PHY specific properties.
                         */
                        reg = <0x0>;
                };
        };
};

This framework is modular and re-usable for other PCIe based Ethernet
devices. It can also be extended to support additional platform specific
information shared across child nodes.

Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com>

Author: Vijayakannan

drivers/ethernet/CMakeLists.txt

@@ -74,3 +74,4 @@ add_subdirectory(phy)
 add_subdirectory(eth_nxp_enet_qos)
 add_subdirectory(nxp_imx_netc)
 add_subdirectory(dwc_xgmac)
+add_subdirectory(intel)

drivers/ethernet/Kconfig

@@ -86,6 +86,7 @@ source "drivers/ethernet/phy/Kconfig"
 
 source "drivers/ethernet/nxp_imx_netc/Kconfig"
 source "drivers/ethernet/Kconfig.renesas_ra"
+source "drivers/ethernet/intel/Kconfig"
 
 endif # "Ethernet Drivers"
 

drivers/ethernet/intel/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Intel Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_ETH_INTEL_PLAT	eth_intel_plat.c)

drivers/ethernet/intel/Kconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config ETH_INTEL_PLAT
+	bool "Intel Ethernet parent Platform device driver"
+	depends on DT_HAS_INTEL_ETH_PLAT_ENABLED
+	help
+	  Enable Platform driver to retrieve the MMIO mapping details and
+	  share them with all the child devices such as MDIO, PHY, MAC
+	  and PTP_CLOCK.

drivers/ethernet/intel/eth_intel_plat.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pcie/pcie.h>
+#include <zephyr/drivers/ethernet/eth_intel_plat.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(intel_eth_plat, CONFIG_ETHERNET_LOG_LEVEL);
+
+#define DT_DRV_COMPAT intel_eth_plat
+
+struct intel_eth_plat_cfg {
+	struct pcie_dev *pcie;
+};
+
+struct intel_eth_plat_data {
+	DEVICE_MMIO_RAM;
+};
+
+uint32_t eth_intel_get_pcie_bdf(const struct device *dev)
+{
+	const struct intel_eth_plat_cfg *cfg = dev->config;
+
+	return cfg->pcie->bdf;
+}
+
+uint32_t eth_intel_get_pcie_id(const struct device *dev)
+{
+	const struct intel_eth_plat_cfg *cfg = dev->config;
+
+	return cfg->pcie->id;
+}
+
+static int intel_eth_plat_init(const struct device *dev)
+{
+	const struct intel_eth_plat_cfg *cfg = dev->config;
+	struct pcie_bar mbar;
+
+	if (cfg->pcie->bdf == PCIE_BDF_NONE ||
+	    !pcie_probe_mbar(cfg->pcie->bdf, 0, &mbar)) {
+		LOG_ERR("Cannot get mbar");
+		return -ENOENT;
+	}
+
+	pcie_set_cmd(cfg->pcie->bdf,
+		     PCIE_CONF_CMDSTAT_MEM | PCIE_CONF_CMDSTAT_MASTER, true);
+
+	device_map(DEVICE_MMIO_RAM_PTR(dev),
+		   mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE);
+
+	return 0;
+}
+
+#define INTEL_ETH_PLAT_CONFIG(n) \
+	static const struct intel_eth_plat_cfg plat_cfg_##n = { \
+		DEVICE_PCIE_INST_INIT(n, pcie), \
+	};
+
+#define INTEL_ETH_PLAT_INIT(n) \
+	DEVICE_PCIE_INST_DECLARE(n); \
+	INTEL_ETH_PLAT_CONFIG(n); \
+	static struct intel_eth_plat_data plat_data_##n; \
+	\
+	DEVICE_DT_INST_DEFINE(n, intel_eth_plat_init, NULL, \
+			      &plat_data_##n, &plat_cfg_##n, POST_KERNEL, \
+			      CONFIG_PCIE_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(INTEL_ETH_PLAT_INIT)

dts/bindings/ethernet/intel,eth-plat.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Ethernet parent platform device.
+
+compatible: "intel,eth-plat"
+
+include: [base.yaml, ethernet-controller.yaml, pcie-device.yaml]

include/zephyr/drivers/ethernet/eth_intel_plat.h

@@ -0,0 +1,35 @@
+/*
+ * Ethernet Platform Utilities for Intel Devices
+ *
+ * This module provides utility functions to interact with the PCIe features
+ * of Intel Ethernet devices, facilitating the retrieval of device-specific
+ * PCIe configuration details such as BDF (Bus/Device/Function) and device ID.
+ *
+ * Copyright (c) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_INTEL_PLAT_H__
+#define ZEPHYR_INCLUDE_DRIVERS_ETH_INTEL_PLAT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Retrieve the PCIe Bus/Device/Function of the device.
+ *
+ * @param dev Pointer to the device structure.
+ * @return PCIe BDF address as a uint32_t.
+ */
+extern uint32_t eth_intel_get_pcie_bdf(const struct device *dev);
+
+/**
+ * @brief Retrieve the PCIe ID of the device.
+ *
+ * @param dev Pointer to the device structure.
+ * @return PCIe ID as a uint32_t.
+ */
+extern uint32_t eth_intel_get_pcie_id(const struct device *dev);
+#endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_INTEL_PLAT_H__ */